JPH0442932A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0442932A JPH0442932A JP2148996A JP14899690A JPH0442932A JP H0442932 A JPH0442932 A JP H0442932A JP 2148996 A JP2148996 A JP 2148996A JP 14899690 A JP14899690 A JP 14899690A JP H0442932 A JPH0442932 A JP H0442932A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- opening
- semiconductor substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高性能かつ高集積化が可能な半導体装置および
その製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device capable of high performance and high integration, and a method for manufacturing the same.
従来の技術
従来、半導体装置たとえばMO8型半導体装置は、第3
図(A)に示すように、一導電型半導体基板1の上にゲ
ート酸化膜6、ゲート電極7!−形成し、さらに反対導
電型不純物を形成後ソース・ドレイン8.9を形成して
半導体素子21を構成17、隣接する半導体素子21間
に接合容量を低減するための絶縁膜22を埋め込み形成
する方法と、第3図(B)に示すように、さらに基板と
の接合容量を低減するために半導体基板1の上に絶縁膜
23を形成し、その上にシリコン単結晶24を形成し、
そこに半導体素子25を形成する方法が行われている。2. Description of the Related Art Conventionally, a semiconductor device, for example, an MO8 type semiconductor device, has a third
As shown in Figure (A), a gate oxide film 6 and a gate electrode 7 are formed on a semiconductor substrate 1 of one conductivity type. - After forming impurities of opposite conductivity type, forming source/drain 8.9 to form semiconductor element 21 17, and embedding insulating film 22 for reducing junction capacitance between adjacent semiconductor elements 21. As shown in FIG. 3(B), an insulating film 23 is formed on the semiconductor substrate 1 in order to further reduce the junction capacitance with the substrate, and a silicon single crystal 24 is formed on the insulating film 23.
A method is being used to form a semiconductor element 25 there.
発明が解決しようとする課題
上記従来法では半導体素子間を一導電型半導体基板1で
接続するか、さらには絶縁膜23で分離されているため
、孤立した複数の半導体素子21.25を同電位に保持
することが困難であり、素子の特性が一定しないという
問題があった。Problems to be Solved by the Invention In the conventional method described above, semiconductor elements are connected by one conductivity type semiconductor substrate 1 or further separated by an insulating film 23, so a plurality of isolated semiconductor elements 21, 25 are placed at the same potential. There was a problem that it was difficult to maintain the temperature and the characteristics of the device were not constant.
本発明は、上述の問題を解決するもので、孤立した半導
体素子の電位を一定に保ち、素子特性の安定した半導体
装置およびその製造方法を提供することを目的とするも
のである。The present invention solves the above-mentioned problems, and aims to provide a semiconductor device in which the potential of an isolated semiconductor element is kept constant and element characteristics are stabilized, and a method for manufacturing the same.
課題を解決するための手段
上記問題を解決するために、本発明の半導体装置は、半
導体素子間を分離する絶縁膜に低抵抗の高融点金属を埋
め込み形成し、前記半導体素子間を接続した構成を備え
たものである。Means for Solving the Problems In order to solve the above problems, the semiconductor device of the present invention has a structure in which a low-resistance, high-melting-point metal is embedded in an insulating film that separates semiconductor elements, and the semiconductor elements are connected. It is equipped with the following.
また、本発明の半導体装置の製造方法は、一導電型半導
体基板上に絶縁膜を形成し、前記絶縁膜に選択的に開口
部を形成して前記半導体基板を露出した後、この露出半
導体基板上にシリコン単結晶を選択成長し、次に前記絶
縁膜に第2の開口部を形成し、この第2の開口部に高融
点金属を絶縁膜厚より薄く形成した後、前記高融点金属
上に第2の絶縁膜を形成し、前記シリコン単結晶に半導
体素子を形成するものである。Further, in the method for manufacturing a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate of one conductivity type, an opening is selectively formed in the insulating film to expose the semiconductor substrate, and then the exposed semiconductor substrate is A silicon single crystal is selectively grown on the insulating film, a second opening is formed in the insulating film, and a refractory metal is formed in the second opening to be thinner than the insulating film. A second insulating film is formed on the silicon single crystal, and a semiconductor element is formed on the silicon single crystal.
さらには、一導電型半導体基板上に高融点金属膜を選択
的に形成した後、全面に絶縁膜を形成し、前記絶縁膜に
選択的に開口部を形成して前記半導体基板を露出し、前
記露出半導体基板上にシリコン単結晶膜を選択成長した
後、前記シリコン単結晶に半導体素子を形成するもので
ある。Furthermore, after selectively forming a high melting point metal film on a semiconductor substrate of one conductivity type, forming an insulating film on the entire surface, and selectively forming an opening in the insulating film to expose the semiconductor substrate, After selectively growing a silicon single crystal film on the exposed semiconductor substrate, a semiconductor element is formed on the silicon single crystal.
作用
上記構成により、孤立した半導体素子の基準電位を絶縁
膜に埋め込んだ高融点金属配線で一定にすることができ
るため、特性の安定した半導体装置を得ることができる
。Effect: With the above configuration, the reference potential of an isolated semiconductor element can be made constant by the high melting point metal wiring embedded in the insulating film, so that a semiconductor device with stable characteristics can be obtained.
実施例 以下本発明の一実施例を図面に基づいて説明する。Example An embodiment of the present invention will be described below based on the drawings.
第1図は本発明の第1の実施例の半導体装置の製造方法
を説明するための工程断面図である。第1図(A)にお
いて、一導電型半導体基板1の上にシリコン酸化膜など
の絶縁膜2をたとえば1ミクロン形成した後、開口部を
形成して半導体基板1を露出させ、第1図(B)に示す
ように、この露出した半導体基板1の上にシリコン単結
晶膜3を選択的に形成する。次に絶縁膜2に第2の開口
部を形成し、この第2の開口部に高融点金属膜4を絶縁
膜2の膜厚より薄く形成する。さらに、高融点金属膜4
の上に第2の絶縁膜5を形成した後、第1図(C)に示
すように、シリコン単結晶膜3の上にゲート酸化膜6、
ゲート電極7、およびソース・ドレイン8,9を形成し
て半導体素子10を構成する。さらに全面に層間絶縁膜
11および選択的に開口部を形成し、この開口部に配線
層12を形成して半導体装置を構成する。FIG. 1 is a process sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1(A), an insulating film 2 such as a silicon oxide film is formed to a thickness of, for example, 1 micron on a semiconductor substrate 1 of one conductivity type, and an opening is formed to expose the semiconductor substrate 1. As shown in B), a silicon single crystal film 3 is selectively formed on this exposed semiconductor substrate 1. Next, a second opening is formed in the insulating film 2, and a high melting point metal film 4 is formed in the second opening to be thinner than the insulating film 2. Furthermore, the high melting point metal film 4
After forming the second insulating film 5 on the silicon single crystal film 3, as shown in FIG. 1(C), a gate oxide film 6,
A gate electrode 7 and source/drains 8 and 9 are formed to constitute a semiconductor element 10. Further, an interlayer insulating film 11 and an opening are selectively formed over the entire surface, and a wiring layer 12 is formed in the opening to form a semiconductor device.
第2図は本発明の第2の実施例の半導体装置の製造工程
を説明する断面図である。第2図(A)において、一導
電型半導体基板1の上に高融点金属膜13をたとえば0
.1 ミクロン形成した後、所定のパターンを通常のフ
ォトエツチング法で形成する。FIG. 2 is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to a second embodiment of the present invention. In FIG. 2(A), a high melting point metal film 13 is placed on a semiconductor substrate 1 of one conductivity type, for example
.. After 1 micron is formed, a predetermined pattern is formed by a normal photoetching method.
次に全面に絶縁膜14を形成した後、選択的に開口部を
形成して半導体基板1を露出させ、第2図(B)に示す
ように、この露出した半導体基板1の上にシリコン単結
晶膜15を選択的に形成する。次に、第2図(C)に示
すように、シリコン単結晶膜15の上にゲート酸化膜6
、ゲート電極7、およびソース・ドレイン8.9を形成
して半導体素子16を構成する。さらに全面に層間絶縁
膜16および選択的に開口部を形成し、この開口部に配
線層17を形成して半導体装置を構成する。Next, after forming an insulating film 14 over the entire surface, an opening is selectively formed to expose the semiconductor substrate 1, and as shown in FIG. A crystal film 15 is selectively formed. Next, as shown in FIG. 2(C), a gate oxide film 6 is formed on the silicon single crystal film 15.
, a gate electrode 7, and a source/drain 8.9 are formed to constitute a semiconductor element 16. Further, an interlayer insulating film 16 and an opening are selectively formed over the entire surface, and a wiring layer 17 is formed in the opening to form a semiconductor device.
なお上記実施例では半導体基板1の上に高融点金属膜4
または13を形成したが絶縁膜間に形成しても良いこと
はいうまでもない。Note that in the above embodiment, a high melting point metal film 4 is provided on the semiconductor substrate 1.
Alternatively, although 13 was formed, it goes without saying that it may be formed between the insulating films.
発明の効果
以上のように、本発明によれば、半導体素子間を絶縁膜
で分離し、かつ必要な半導体素子間を高融点金属の埋め
込み配線で接続するため、各半導体素子間の電位が一定
し、かつ安定した特性が得られる。しかも配線金属を埋
め込んで形成するため高密度の半導体装置を形成するこ
とができるという効果を有するものである。Effects of the Invention As described above, according to the present invention, since semiconductor elements are separated by an insulating film and necessary semiconductor elements are connected by embedded wiring made of high melting point metal, the potential between each semiconductor element is constant. and stable characteristics can be obtained. Furthermore, since the wiring metal is embedded and formed, it has the effect that a high-density semiconductor device can be formed.
第1図は本発明の第1の実施例を説明するための構造断
面図、第2図は本発明の第2の実施例を説明するための
構造断面図、第3図は従来例を説明するための構造断面
図である。
1・・・半導体基板、2. 5.11・・・絶縁膜、3
・・・シリコン単結晶膜、4・・・高融点金属膜、10
・・・半導体素子、12・・・配線層、13・・・高融
点金属膜、14.16・・・絶縁膜、15・・・シリコ
ン単結晶膜、17・・・配線層。
代理人 森 本 義 弘
第1図Fig. 1 is a structural cross-sectional view for explaining the first embodiment of the present invention, Fig. 2 is a structural cross-sectional view for explaining the second embodiment of the present invention, and Fig. 3 is a structural cross-sectional view for explaining the conventional example. FIG. 1... semiconductor substrate, 2. 5.11... Insulating film, 3
...Silicon single crystal film, 4...High melting point metal film, 10
... Semiconductor element, 12... Wiring layer, 13... High melting point metal film, 14.16... Insulating film, 15... Silicon single crystal film, 17... Wiring layer. Agent Yoshihiro MorimotoFigure 1
Claims (1)
する絶縁膜に沿って前記半導体素子間を接続する高融点
金属配線を設けた半導体装置。 2、一導電型半導体基板上に絶縁膜を形成し、前記絶縁
膜に選択的に開口部を形成して前記半導体基板を露出し
た後、この露出半導体基板上にシリコン単結晶を選択成
長し、次に前記絶縁膜に第2の開口部を形成し、この第
2の開口部に高融点金属を前記絶縁膜厚より薄く形成し
た後、前記高融点金属上に第2の絶縁膜を形成し、前記
シリコン単結晶に半導体素子を形成する半導体装置の製
造方法。 3、一導電型半導体基板上に高融点金属膜を選択的に形
成した後、全面に絶縁膜を形成し、前記絶縁膜に選択的
に開口部を形成して前記半導体基板を露出し、前記露出
半導体基板上にシリコン単結晶膜を選択成長した後、前
記シリコン単結晶に半導体素子を形成する半導体装置の
製造方法。[Scope of Claims] 1. A semiconductor device provided with a high-melting point metal wiring that connects semiconductor elements along an insulating film that separates semiconductor elements formed on a semiconductor substrate of one conductivity type. 2. Forming an insulating film on a semiconductor substrate of one conductivity type, selectively forming an opening in the insulating film to expose the semiconductor substrate, and selectively growing a silicon single crystal on the exposed semiconductor substrate; Next, a second opening is formed in the insulating film, a refractory metal is formed in the second opening to be thinner than the insulating film, and a second insulating film is formed on the refractory metal. . A method for manufacturing a semiconductor device, which comprises forming a semiconductor element on the silicon single crystal. 3. After selectively forming a high melting point metal film on a semiconductor substrate of one conductivity type, forming an insulating film on the entire surface, selectively forming an opening in the insulating film to expose the semiconductor substrate, and A method for manufacturing a semiconductor device, which comprises selectively growing a silicon single crystal film on an exposed semiconductor substrate, and then forming a semiconductor element on the silicon single crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2148996A JP2515040B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2148996A JP2515040B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0442932A true JPH0442932A (en) | 1992-02-13 |
| JP2515040B2 JP2515040B2 (en) | 1996-07-10 |
Family
ID=15465376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2148996A Expired - Fee Related JP2515040B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515040B2 (en) |
-
1990
- 1990-06-06 JP JP2148996A patent/JP2515040B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2515040B2 (en) | 1996-07-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |