JPH0442937A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve hot carrier resistance and improve current driving capacity by the reduction of parasitic resistance by implanting ions for forming the diffusion layer in low impurity concentration, and then performing high temperature heat treatment in oxygen atmosphere or in the oxygen atmosphere diluted by inert gas. CONSTITUTION:Phosphorous ions are implanted with a gate electrode 3 as a mask. Next, it is annealed in oxygen atmosphere or diluted oxygen atmo sphere by inert gas, whereby the implanted phosphorous ions are oxidated, accelerated, and diffused, and n<-> layers 6 and 7 are formed. By such oxidation, acceleration, and diffusion, the phosphorous ions diffuse to enough depth below the gate electrode 3 too. In this case, the n<-> layers 6 and 7 overlaps the gate electrode over the distance of 0.05 mum or more. Next, with a thick silicon oxide film 8 formed around the gate electrode 4 as a sidewall mask, arsenic ions are implanted, and usual heat treatment is applied to form a source 9 and a drain 10 consisting of n+ continuous from the n<-> layers 6 and 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly an LD in which a domain is composed of a region with a low impurity concentration and a region with a high impurity concentration.
The present invention relates to a method for manufacturing a D-structure MOSFET.

(Prior Art) Conventionally, in a MOSFET having a fine structure, source/drain expansion HI1. An LDD (Lightly Doped Drain) structure in which a low impurity concentration diffusion layer (n-layer, p-layer) is sandwiched between the RFI and the channel region is generally widely used. In a MOSFET having such an LDD structure, this low impurity concentration diffusion layer does not undergo 17% impurity diffusion due to its low concentration, and therefore lateral diffusion is small, so it does not extend sufficiently to the bottom of the gate electrode. Not yet. Therefore, the n-layer does not overlap sufficiently with the gate electrode. Moreover, when polysilicon is used for the gate electrode, a post-oxidation film is formed on the polysilicon surface and sidewalls after gate processing, so the gate electrode portion is reduced accordingly, and the overlap tends to become smaller. If the amount of overlap between the gate electrode and the n-layer is too small, the resistance to hot carriers decreases and the parasitic resistance of the transistor increases, resulting in a decrease in current drive capability.

Recently, in order to further improve hot carrier resistance, ions have been implanted into low concentration layers with higher energy and deeper implantation, so the problem of difficulty in eliminating overlap is becoming more and more serious.

In order to eliminate such drawbacks, improve hot carrier resistance, suppress the generation of parasitic resistance, and improve current drive ability, the gate electrode and a diffusion layer with low impurity concentration such as an n-layer are intentionally formed. Gate overlapped with /n
- Overlap LDD structure has been proposed,
For example, the IEEE, T
RANSACTIONS ON ELECT-RON
DEVICES, VOL, 35. NO, 12, P
P, 2088-2093, etc.

(Problem to be solved by the invention) The above-mentioned IEEE TRANSACTIONS ON
ELECTl? ON I) Gate-Drain 0verlappedDe described in EVI-CBS
In VICE (GOLD), after forming an oxide film on a polysilicon film, the polysilicon film is under-etched to form a trapezoidal gate electrode with a long base, and then phosphorus is ion-implanted to form an n- The layer is formed to extend to the bottom of the gate electrode to obtain overlap, and then sidewalls are formed on the sides of the gate electrode and oxide film, and arsenic is ion-implanted at a high concentration. n
It is made to form a layer. Such a method has the disadvantage that the process is complicated, leading to increased costs, and it is also difficult to control the dimensions and shape.

The object of the present invention is to eliminate the above-mentioned conventional drawbacks and to
In a MOSFET with this structure, the low concentration drain layer and gate electrode can be sufficiently overlapped,
Moreover, the present invention aims to provide a method for manufacturing a semiconductor device with simple steps and high yield.

(Means and Effects for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes the steps of: - forming a gate electrode on the surface of a conductive type semiconductor substrate via a gate insulating film; and masking the gate electrode. A process of implanting impurities of opposite conductivity type into a semiconductor substrate, and performing high-temperature heat treatment on this semiconductor substrate in an oxygen atmosphere or an oxygen atmosphere diluted with an inert gas to accelerate oxidation of the impurities implanted here. A step of forming a low impurity concentration diffusion layer by diffusion under the gate electrode so as to obtain an overlap amount of at least 0.05 μm, and a masking effect for ion implantation on the side surface of the gate electrode. The method is characterized by comprising a step of forming a sidewall, and a step of implanting and diffusing impurities of opposite conductivity type at a high concentration using the gate electrode and the sidewall as a mask to form a source and a drain. It is something.

In the method of the present invention, after performing ion implantation to form a diffusion layer with a low impurity concentration, a high temperature heat treatment is performed in an oxygen atmosphere or an oxygen atmosphere diluted with an inert gas. Accelerated diffusion occurs, and the impurity diffuses with a diffusion coefficient 4 to 5 times higher than in the case of normal diffusion, and is diffused deep below the gate electrode.Meanwhile, oxygen is diluted with an inert gas. In this case, the oxidation rate is low, and the thickness of the oxide film on the surface of the gate electrode can be kept small.Therefore, by this method, the amount of overlap with the gate electrode can be increased.

FIG. 1 compares the growth rate of an oxide film and the diffusion rate of impurities during high-temperature heat treatment as a function of the oxygen dilution concentration in the atmosphere. The oxidation rate is proportional to the first power of the oxygen concentration, but the impurity diffusion rate is proportional to the oxygen concentration (
That is, the change is proportional to the 0.5th power of the oxidation rate. Therefore, in order to increase the gate/drain overlap, it is better to reduce the oxygen concentration and slow the oxidation rate so that the impurity diffusion distance can be increased compared to the post-oxidation film thickness of the polysilicon. - It turns out to be advantageous.

(Embodiment) FIG. 2 shows the structure of a semiconductor device in successive steps T in an embodiment of the method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 2A, a silicon oxide film 2 constituting a gate insulating film is uniformly formed on the surface of a P-type silicon semiconductor substrate 10 to a thickness of 200 mm, and then polysilicon is deposited by CVD. A film is deposited to a thickness of 4000 nm, and patterned and processed by photoetching to form the gate electrode 3. Next, as shown in FIG. 2B, the silicon oxide film 2 is removed by etching, leaving the gate oxide film 4 on the lower part of the gate electrode 3, and then an oxidation treatment is applied to the surface of the silicon substrate 1 and the surface of the silicon substrate 1. A thin silicon oxide film 5 having a thickness of 100 nm is formed on the surface of a gate electrode 3 made of polysilicon. Subsequently, as shown in FIG. 2C, phosphorus ions are implanted at an energy of 70 KeV using the gate electrode 3 as a mask.

The phosphorus ion concentration at this time is set to about 2×10'' atoms/cm. Next, annealing is performed in an oxygen atmosphere or a diluted oxygen atmosphere with an inert gas, and the implanted phosphorus ions are oxidized and diffused to accelerate n-)i! 6 and 7 are formed. In this example, C10, this annealing is performed using an inert gas such as nitrogen or argon in oxygen at a partial pressure ratio of 50%.
The semiconductor substrate 1 is heated at 90° C. in a diluted oxygen atmosphere containing
Heat treatment is performed at a temperature of 0'C for about 1 hour. This oxidation-enhanced diffusion can also be performed in an oxygen atmosphere, and in this case, heat treatment may be performed at a temperature of 900 to 950° C. for about several tens of minutes. Due to such oxidation-enhanced diffusion, the diffusion coefficient of phosphorus ions becomes 4-5 times larger than that of thermal diffusion in a normal non-oxidizing atmosphere, and therefore the phosphorus ions are diffused to a sufficient depth below the gate electrode 3. I will do it. in this case,
It is sufficient that the n-layers 6 and 7 overlap the gate electrode over a distance of 0.05 .mu.- or more. Further, due to this oxidation accelerated diffusion, the silicon oxide film 5 becomes thick to about 200 to 300 layers, and at the same time, the gate electrode 3 made of polysilicon is also oxidized, but since polysilicon is oxidized faster than silicon, the gate electrode 5 becomes thicker. An even thicker oxide film (200 to 500 layers) will be formed around it.

Next, as shown in FIG. 2E, arsenic ions are implanted using the thick silicon oxide film 8 formed around the gate electrode 4 as a Zyte wall mask, and a normal heat treatment is performed.
-A source 9 and a drain 10 made of an n' layer continuous with N6 and N7 are formed. After that, the process is normal! 1
Since this is the same as the case of forming an 0SFET, detailed explanation will be omitted.

As described above, in the present invention, phosphorus ions are deeply diffused to the lower side of the gate electrode 4 by oxidation-enhanced diffusion to form a low impurity concentration diffusion layer. (St
anford University Process
HngineeringModel) is given as the following equation.

D= Do X(1+Oed, fact) ---(1
) Here, D is the diffusion coefficient when there is no oxidation-enhanced diffusion,
Oed and fact are given by the following equation (2) and are coefficients related to oxidation speed increase. , Oed, fact is the following equation (2)
As shown in , it has a value proportional to the 0.5th power of the oxidation rate, so it takes an extremely small value in a non-oxidizing atmosphere, but a large value in an oxidizing atmosphere.

Oed, fact=[FIl, OX exp(-FIN
, E/(kT))X (OED, KOXexp(-0E
D, KE/(kT)) x a x m m x / d
t)°ED, *kTE] ----(2) Here, when using a silicon substrate 1 with a plane orientation of (100) and performing heat treatment in a dry oxygen atmosphere to diffuse phosphorus ions, the following will occur. It is possible to adopt numerical values such as .

FIl, O=5.50 FI1. E=0.57eν OED, KO=2.86X10th edition' sin/μm0E
D, KE=-5,64eV dXmax/dt= (oxidation rate gm 7mlre)
OED, RATE=0.5 -8,36X 10-5eV/K
The results calculated in a dry oxidizing atmosphere (Oz 190%) at °C are shown in the following table.

As can be seen from this result, in oxidation-enhanced diffusion,
The diffusion coefficient is 4 to 5 times that of normal diffusion,
It is confirmed that phosphorus ions diffuse to the lower side of the gate electrode and a sufficiently large amount of overlap can be obtained.

Further, if the heat treatment is performed in an oxygen atmosphere diluted with an inert gas, impurity diffusion can be effectively performed without increasing the thickness of the oxide film on the gate electrode surface.

As shown in Figure 1, the oxidation rate is proportional to the first power of the oxygen concentration, but the impurity diffusion rate changes in proportion to the 0.5th power of the oxygen concentration (that is, the oxidation rate), as described by the SUPREM model. shows.

Therefore, in order to increase the gate/drain overlap, it is better to reduce the oxygen concentration and slow the oxidation rate to achieve a larger impurity diffusion distance than the post-oxidation film thickness of polysilicon. It turns out to be advantageous. Therefore, by performing high-temperature heat treatment in a dilute oxidation atmosphere after n-layer ion implantation, LDD MOS with sufficient gate/drain overlap can be manufactured.
FET can be realized by a simple method.

The present invention is not limited to the embodiments described above, and can be modified and modified in many ways. For example, in the above-described embodiment, during the oxidation enhanced diffusion process, ion implantation was performed to form the n layer using the thick oxide film formed on the surface of the gate electrode made of polysilicon as a sidewall. After the rapid diffusion process, the silicon oxide film can be removed, or sidewalls can be formed on the sides of the gate electrode again on the silicon oxide film.

(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device according to the present invention, ion implantation is performed to obtain a low impurity concentration layer of an LDD structure using the gate electrode as a mask, and then an oxygen atmosphere is implanted. A low impurity concentration layer can be formed by performing high-temperature heat treatment in an oxygen atmosphere diluted with a medium or an inert gas, and at the same time as recovery oxidation, ions are diffused deep below the gate electrode by oxidation-enhanced diffusion. As a result, the overlap between the gate and the drain can be set to 0.05 .mu.m or more, and hot carrier resistance can be improved, and the current drive capability can be improved by reducing parasitic resistance. In addition, there is no need to create a special layer or perform ion implantation diagonally to increase the amount of overlap, so the manufacturing process is not complicated, improving yield and reliability. I will do it.

[Brief explanation of drawings]

FIG. 1 is a graph plotting the relationship between oxidation rate and impurity diffusion rate in high-temperature heat treatment against oxygen dilution concentration. FIG. 3 is a diagrammatic cross-sectional view showing the sequential steps of the example. 1... Silicon semiconductor substrate 2... Silicon oxide film 3... Gate electrode 4...
・Gate oxide film 6, 7...N- layer 8...Silicon M conversion H9...Source 11...Drain Fig. 1 Fig. 2

Claims (1)

[Claims] 1. A step of forming a gate electrode on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a step of implanting an impurity of the opposite conductivity type into the semiconductor substrate using this gate electrode as a mask. Then, this semiconductor substrate is subjected to high-temperature heat treatment in an oxygen atmosphere or an oxygen atmosphere diluted with an inert gas, and the impurities implanted here are transferred to the lower side of the gate electrode by at least 0.05 μm by oxidation-enhanced diffusion. forming a diffusion layer with a low impurity concentration by diffusion to obtain an overlapping amount of ions; forming a sidewall having a masking effect against ion implantation on a side surface of the gate electrode; A method for manufacturing a semiconductor device, comprising the step of implanting and diffusing impurities of opposite conductivity type at a high concentration using a wall as a mask to form a source and a drain.