JPH0442939A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To equalize the element characteristics between lots (wafers) by a method wherein low concentration diffused layers are stably formed beneath a gate electrode in the relatively easy process in excellent controllability. CONSTITUTION:A polysilicon film 4 and a silicon oxide film 5 are successively formed by CVD process while a high melting point film 7 is buried in the opening part 6 formed in the silicon oxide film 5 by laser irradiation process and then after removing the silicon oxide film 5, low concentration diffused layers 8 are formed by ion-implantation process using the metallic film 7 as a mask. Through these procedures, the thin part of the polysilicon film 4 whereon the high melting point metallic film 7 is not formed can be formed by a process in excellent film thickness controllability such as the CVD process etc. so that the film 7 may be formed in proper film thickness for preventing ions from reaching the substrate 1 beneath the film 7. Resultantly, the low concentration diffused layers 8 can be stably formed in excellent controllability beneath a gate electrode 10.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, it is possible to stably form a low concentration diffusion layer under a gate electrode with good controllability and in a relatively simple process, and to form a low concentration diffusion layer between lofts (wafer The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can make device characteristics almost uniform in the following steps: forming a gate insulating film on a base film; and forming a first conductive film on the gate insulating film. a step of forming a film having an etching selectivity with respect to the first and second conductive films on the first conductive film, and selectively forming a film having the etching selectivity with respect to the first and second conductive films. a step of forming an opening by etching, a step of forming a second conductive film on the entire surface, a step of embedding the second conductive film in the opening by laser irradiation, and a step of forming a film having the etching selectivity. a step of introducing ions of a conductivity type opposite to that of the underlying film into the underlying film using the second conductive film as a mask to form a low concentration diffusion layer; a step of forming an insulating film to cover the conductive film; a step of peeling off the insulating film to form a sidewall insulating film on the sidewall of the second conductive film; selectively etching the first conductive film using the sidewall insulating film as a mask to form a gate electrode composed of the first and second conductive films; and the second conductive film and the sidewall. Source/train diffusion consisting of a low concentration diffusion layer and a high concentration diffusion layer is achieved by introducing ions of the opposite conductivity type into the underlying film using the insulating film as a mask to form a high concentration diffusion layer. or a step of forming a gate insulating film on a base film, a step of forming a first conductive film on the gate insulating film, and a step of forming a first conductive film on the gate insulating film. forming a film having an etching selectivity with respect to the first and second conductive films on the conductive film; and forming an opening in the film having the etching selectivity by selectively etching the film having the etching selectivity. , a step of forming a second conductive film on the entire surface, and! 7. A step of embedding a second conductive film in the opening by means of a laser beam, a step of removing the film having a selective pattern of 7,000 degrees, and a step of embedding a second conductive film in the opening using the second conductive film as a mask. a step of introducing ions of a conductivity type opposite to that of the underlying film into the underlying film to form a low-temperature diffusion layer; a step of forming an insulating film to cover the second conductive film; forming a sidewall insulating film on the sidewall of the second conductive film by cutting the insulating film seven times; forming a source/drain diffusion layer consisting of a low concentration diffusion layer and a high concentration diffusion layer by introducing conductive type ions into the underlying film to form a high concentration diffusion layer; selectively etching the first conductive film using the second conductive film and the sidewall insulating film as a mask to form a gate electrode made of the first and second conductive films. Configure.

[Industrial application field]

The present invention provides MO31 to MO31 of LDD structure in which the gate electrode is arranged not only on the channel region but also on the low concentration diffusion layer.
The present invention can be applied to a method of manufacturing a transistor, and particularly relates to a method of manufacturing a semiconductor device that can stably form a low concentration diffusion layer with good controllability.

recent years,! 1. , 10s) With the miniaturization of transistors, the photoelectron effect due to the increase in the internal electric field t has become a problem. To solve this problem, a so-called LDD structure has been adopted in which a low concentration diffusion layer is provided at the end of the train to widen the depletion layer and alleviate the internal electric field from devices with a gate length of about 1 μm or less. This L
According to the DD structure, it has become possible to suppress the amount of Bot I, D1/Li L, and Ron generated, but it is still not possible to completely suppress it.

As will be described later, in the current manufacturing method, the upper part of the low concentration diffusion layer is the sidewall insulating film (sidewall) which becomes a thin layer formed on the sidewall of the gate electrode, so the area near the interface with the silicon substrate below the sidewall insulating film The charge generated by the carriers pinches off the low-concentration diffusion layer, resulting in high resistance, and as a result, the transconductance of the transistor g.

The weight was greatly reduced. For this reason, the current LDD structure is effective without significantly reducing the amount of hot carriers generated, but for the same amount of hot carriers generated, It had a structure with lower resistance than the usual single drain structure.

Therefore, there is a need for a method of manufacturing a transistor with an i-DD structure that is not easily affected by charges generated by hot carriers.

[Conventional technology]

FIGS. 4(a) to 4(C) are diagrams illustrating a conventional method for manufacturing a semiconductor device. The manufacturing method shown in FIG.
This is the case when applied to an O3I-transistor. In FIG. 4, 31 is a p-type substrate made of Si etc., 32 is a gate insulating film made of SiO□ etc., 33 is a gate electrode made of polySR etc., 34 is a silicon oxide film made of S 10 z etc. 35 is, for example, an n-type low concentration diffusion layer, 36
is a side wall made of SiO□, etc., and 37 is, for example, r
The Vi-type high concentration diffusion layer 38 is a source/train diffusion layer consisting of a low concentration diffusion layer 35 and a high concentration diffusion layer 37.

Next, the manufacturing method will be explained.

First, as shown in FIG. 4(a), after sequentially depositing Sin and poly-Sl on a p-type silicon substrate 31 by, for example, the CVD method, poly-Si and SiO□ are selectively etched by, for example, etching. By etching, a gate electrode 33 and a -1° insulating film 32 are formed.

Next, as shown in FIG. 4(b), after oxidizing the substrate 31 and the gate electrode 33 by, for example, heat or oxidation to form a silicon oxide film 34, the gate electrode 33 is used as a mask by, for example, P ion implantation. U7 through the silicon oxide film 34 1
．． Then, P' is introduced into the substrate 31 to form an n-type low concentration diffusion layer 35.

Then, after depositing Sin on the entire surface so as to cover the gate electrode 33 by, for example, the CVD method, the S t Oz is etched back by, for example, RIE to form a side wall 36 on the side wall of the gate electrode 33, and the gate electrode After exposing the silicon oxide film 33, for example, P is ion-implanted through the silicon oxide film 34 using the gate electrode 33 and the sidewall 36 as a mask.

By introducing this to form the high concentration diffusion layer 37, a source/drain diffusion layer 38 consisting of a low concentration diffusion layer 35 and a high concentration diffusion layer 37 as shown in FIG. 4(c) can be obtained.

The conventional manufacturing method described above has the advantage that by forming the low concentration diffusion layer 35, the internal electric field can be relaxed and the hot electron effect can be suppressed. However, since the sidewall 36 serving as an insulating spacer is formed above the low concentration diffusion layer 35, charges generated by hot electrons are accumulated there, and this charge depletes the low concentration diffusion layer 35, and As a result, there is a drawback that the mutual conductance g1 deteriorates significantly as the operating time passes.

In order to avoid the above-mentioned deterioration of the mutual conductance g, an LDD structure is conventionally known in which a gate electrode 33 is arranged also above the low concentration diffusion layer 35, as shown in FIG. In FIG. 5, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, 41 is a field oxide film made of SiO□, etc., and 42 is, for example, an n-type channel stopper.

With such an LDD structure, even if hot carriers are generated and charges are generated in the gate oxide film 32, the electric field by the gate electrode 33 acts dominantly, so that large deterioration of the mutual conductance g is prevented. This has the advantage that the life span is 103 times longer than that shown in FIG. 4.

Next, as shown in FIG. 4, a method for manufacturing a semiconductor device in which a gate electrode 33 is also formed above the low concentration diffusion layer 35 will be described.
This will be explained in detail below using the drawings.

FIGS. 6(a) to 6(f) are diagrams illustrating another example of the conventional method for manufacturing a semiconductor device. The manufacturing method of the illustrated example is 19
1986 academic journal rTechnical Digesto
f International Electron
Devices Meeting JP, 742 (
Reported by: Tiao-Yuao Huang et al. In FIG. 6, the same reference numerals as in FIG. 4 indicate the same or corresponding parts, 51 is a polysilicon film, 51a
52 is a mask layer made of resist or the like; 53 is an insulating film made of 5in2 or the like;
a is a side wall made of SiO□ or the like.

Next, the manufacturing method will be explained.

First, as shown in FIG. 6(a), poly-Si is deposited on a p-type silicon substrate 31 by thermal oxidation and CVD to form a gate insulating film 32 and a polysilicon film 51. A mask layer 52 is formed on the silicon film 51 by patterning a resist.

Next, as shown in FIG. 6(b), the polysilicon film 52 is selectively etched using the mask layer 52, for example, by RIE. At this time, a convex portion 51 is formed on the polysilicon film 51.
A is formed, and a polysilicon film 51 having a thickness thinner than that of the convex portion 51a is left on the gate insulating film 32 except for the convex portion 51a. Next, mask layer 52 is removed.

Next, as shown in FIG. 6C, P is introduced into the substrate 31 by, for example, ion implantation of P, using the convex portion 5ia of the polysilicon film 51 as a mask, and the n-type low concentration diffusion layer 3 is introduced into the substrate 31.
form 5.

Next, as shown in FIG. 6(d), an insulating film 53 is formed by depositing 5 iOz over the entire surface by, for example, the CVD method so as to cover the convex portions 51a.

Next, as shown in FIG. 6(e), after etching back the insulating film 53 by, for example, RIE to form a side wall 53a on the side wall of the convex part 51a, the convex part 51a and the side wall 53a are masked by, for example, RIE. The polysilicon 51 is selectively etched as a gate insulating film 32.
expose. At this time, an inverted T-shaped gate electrode 33 made of poly-Si and having a convex portion 51a is formed.

Then, for example, As is ion-implanted into the substrate 31 using the convex portion 51a and the sidewall 53a as a mask.
By introducing the n-type high concentration diffusion layer 37, the source/drain diffusion [3] consisting of the low concentration diffusion layer 35 and the high concentration diffusion layer 37 as shown in FIG.
You can get 8.

If the above manufacturing method is used, J of low concentration diffusion IJ35,
Since the gate electrode 33 can be formed on both sides, there is an advantage that large deterioration of the mutual conductance g can be prevented.

[Problems to be Solved by the Invention 1 to 1] However, in the conventional semiconductor device manufacturing method shown in FIG. 51
There was a problem that the thickness control became unstable. For this reason, the low concentration diffusion layer 35 formed by ion implantation cannot be formed stably with good controllability, and there is a problem that device characteristics vary between lofts (within a wafer).

Therefore, the present invention makes it possible to stably form a low concentration diffusion layer under the electrode rod with good controllability and in a relatively simple process, and to make device characteristics almost uniform between lots (within a wafer). The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can perform the following steps.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the first invention includes a step of forming a gate insulating film on an underlying film (a substrate such as Si, a semiconductor layer, a well, etc.), and forming a first conductive film on the first conductive film, forming a film having an etching selectivity with respect to the first and second conductive films, and having the etching selectivity with the first conductive film. selectively etching the membrane to form an opening;
a step of forming a second conductive film on the entire surface; a step of embedding the second conductive film in the opening by laser irradiation; a step of removing the film having the etching selectivity;
A step of introducing ions of a conductivity type opposite to that of the underlying film into the underlying film using the conductive film as a mask to form a low concentration diffusion layer, and forming an insulating film to cover the second conductive film. forming a sidewall insulating film on the sidewall of the second conductive film by etching back the insulating film; and etching back the first conductive film using the second conductive film and the sidewall insulating film as a mask. selectively etching the conductive film to form a gate electrode made of the first and second conductive films; and etching the underlying film using the second conductive film and the sidewall insulating film as a mask. and forming a source/drain diffusion layer consisting of a low concentration diffusion layer and a high concentration diffusion layer by introducing ions of the opposite R type into the underlying film to form a high concentration diffusion layer. It is something that

In order to achieve the above object, the method for manufacturing a semiconductor device according to the second invention includes a step of forming a gate insulating film on an underlying film (a substrate such as Si, a semiconductor layer, a well, etc.), and a step of forming a gate insulating film on the gate insulating film. a step of forming a first conductive film on the first conductive film, a step of forming a film having an etching selectivity with respect to the first and second conductive films, and a step of forming a film having the etching selectivity with respect to the first and second conductive films. A step of selectively etching to form an opening, a step of forming a second conductive film on the entire surface, a step of embedding the second conductive film in the opening by laser irradiation, and the etching selectivity. a step of forming a low concentration diffusion layer by introducing ions of a conductivity type opposite to that of the underlying film into the underlying film using the second conductive film as a mask; forming an insulating film to cover the second conductive film; etching back the insulating film to form a sidewall insulating film on the sidewall of the second conductive film; A source consisting of a low concentration diffusion layer and a high concentration diffusion layer is formed by introducing ions of a conductivity type opposite to that of the underlying film into the underlying film using the film and sidewall insulating film as a mask to form a high concentration diffusion layer. / forming a drain diffusion layer, and selectively etching the first conductive film using the second conductive film and the sidewall insulating film as a mask to remove the first and second conductive films. The method includes a step of forming a gate electrode.

[Effect]

In the present invention, as will be described later in the Examples, the thin part of the inverted 1-shaped gate electrode is formed by a method with good film thickness controllability, such as the CVD method, and as a result, a low concentration diffusion layer can also be formed. It will be formed with good reproducibility.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(1) are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention. In Figure 1,
1 is a p-type substrate made of Si, etc., 2 is a field oxide film made of SiO□, etc., 3 is a gate insulating film made of STOx, etc., 4 is a polysilicon film, and 5 is a silicon oxide film made of SiO□, etc. 6 is an opening formed in the silicon oxide film 5, 7 is a high melting point metal film made of Ti or the like, 8 is an n-type low concentration diffusion layer, 9 is an insulating film made of Stow etc., 9a is 5ift etc. 10 is a polysilicon film 4 and a high melting point metal film 7.
11 is an n+ type high concentration diffusion layer, 12 is a source/drain diffusion layer consisting of a low concentration diffusion layer 8 and a high concentration diffusion layer 11, 13 is an insulating film between the eyebrows made of PSG or the like, and 14 is an interlayer. The contact hole 15 formed in the insulating film 13 is An! This is a wiring layer made of -3i or the like.

Next, the manufacturing method will be explained.

First, as shown in FIG. 1(a), a p-type silicon substrate 1 is oxidized by the LOCOS method to a film thickness of, for example, 600 nm.
After forming the n+ field oxide film 2, the substrate I is oxidized by, for example, thermal oxidation to form a gate insulating film 3 having a thickness of, for example, 15 nm.

Next, as shown in FIG. 1(b), poly-Si is deposited over the entire surface by, for example, the CVD method to form a polysilicon film 4 having a film thickness of, for example, 1100 nm. Then, Si is deposited on the polysilicon film 4 by, for example, the CVD method.
A silicon oxide film 5 having a thickness of, for example, 300 na+ is formed by depositing ng.

Next, as shown in FIG. 1(d), the silicon oxide film 5 is selectively etched by, for example, RIE to form an opening 6, and the polysilicon film 4 is exposed within the opening 6.

Next, as shown in FIG. 1(e), Ti is deposited on the entire surface by sputtering, for example, to form a high melting point metal film 7 having a thickness of, for example, 100 ns+.

Next, as shown in FIG. 1(f), for example, ArF excimer laser irradiation is performed to melt the high melting point metal film 7, thereby filling the opening 6 with the high melting point metal film 7.

Next, as shown in FIG. 1(g), the silicon oxide film 5 is removed by lift-off, for example, by wet etching. At this time, the high melting point metal film 7 on the silicon oxide film 5 is also removed.

Next, as shown in FIG. 1(h), for example, by ion implantation of P, using the high melting point metal film 7 as a mask, for example, Po of the opposite conductivity type to the substrate 1 is implanted, for example, 1×IQ "am-", 40
KeV is introduced into the substrate 1 to form an n-type low concentration diffusion layer 8.

Next, as shown in FIG. 1(i), SiO□ is deposited to cover the high melting point metal film 7 by, for example, the CVD method to form a silicon oxide film 9 having a thickness of, for example, 200 nm*.

Next, as shown in FIG. 1(j), after etching back the silicon oxide film 9 by, for example, RIE to form a sidewall insulating film 9a on the side wall of the high melting point metal film 7, the high melting point metal film 7 is etched back by, for example, RTE. Then, using the sidewall insulating film 9a as a mask, the polysilicon film 4 is selectively etched to form the gate insulating film 3.
expose.

At this time, a gate electrode 10 made of a polysilicon film 4 and a high melting point metal film 7 is formed.

Next, as shown in FIG. 1(k), for example, As is ion-implanted, using the high melting point metal film 7 and the side wall insulating film 9a as a mask, a conductivity type of As'' opposite to that of the substrate 1 is implanted, for example, by 4X.
10"elm-" and 70 KeV are introduced into the substrate 1 to form an n' type high concentration diffusion layer 11.

At this time, a source/drain diffusion layer 12 consisting of a low concentration diffusion layer 8 and a high concentration diffusion layer 11 is formed.

After forming the eyebrow insulating film 13 made of PSG and forming the contact holes 14 in the interlayer insulating film thickness 3, wiring layers made of A1 are formed so as to make contact with the source/drain diffusion layers 12 in the contact holes 14. By forming 15, a semiconductor device as shown in FIG. 1(f) can be obtained.

That is, in this embodiment, a polysilicon film 4 and a silicon oxide film 5 are sequentially formed by the CVD method, and a high melting point metal film 7 is buried in the opening 6 formed in the silicon oxide film 5 by laser irradiation, and the silicon oxide film is After removing 5, low-concentration diffusion N8 is formed by ion implantation using the high melting point metal film 7 which becomes the convex portion on the polysilicon film 4 as a mask. In this way, the high melting point metal film 7 is formed with an appropriate thickness such that no ions reach the substrate 1 below, and the polysilicon film 4 on which the high melting point metal film 7 is not formed is thin. Since the portion is formed by a method with good film thickness controllability, such as the CVD method, as a result, a low concentration diffusion layer can be stably formed under the gate electrode 10 with good controllability. Therefore, a structure in which the gate electrode exists even on the low concentration diffusion layer 8 which has excellent hot carrier resistance can be formed with good controllability, and device characteristics can be made almost uniform between lofts (wafers). It can contribute to improving the performance of the circuit.

In this embodiment, the case where the high concentration diffusion layer 11 is formed after etching the polysilicon film 4 has been described, but the present invention is not limited to this, and the second
As shown in FIGS. (a) and (b), before etching the polysilicon film 4, a high concentration diffusion layer 11 is formed by ion implantation using the high melting point metal M7 and the sidewall insulating film 9a as a mask (at this time, source/drain diffusions 1i12 are formed), and the polysilicon film 4 is etched using the high melting point metal film 7 and sidewall insulating film 9a as a mask, and the gate electrode 10 is formed). In this embodiment, the high melting point metal film 7 is deposited on the entire surface, the high melting point metal film 7 is buried in the opening 6 by irradiation with I/- laser, and the silicon oxide film 5 is removed. Although explained, the present invention is not limited to this, and FIG. 3(a),
As shown in (b), a high melting point metal film 7 is deposited on the entire surface,
Patterning the high melting point metal film 7 into a shape including the opening 6,
The silicon oxide film 5 may be removed by irradiating a laser to embed the high melting point metal film 7 in the opening 6. In this case, when the silicon oxide film 5 is finally removed, this silicon oxide film This is preferable because the high melting point metal film 7 can be reliably removed without remaining on the film 5.

〔Effect of the invention〕

According to the present invention, a low concentration diffusion layer can be stably formed under a gate electrode with good controllability and in a relatively simple process, and device characteristics can be made almost uniform between lofts (within a wafer). It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the manufacturing method of one embodiment of the semiconductor device manufacturing method according to the present invention, FIGS. 2 and 3 are diagrams for explaining the manufacturing method of other embodiments, and FIG. 4 is the conventional 5 is a cross-sectional view showing the structure of an LDD structure transistor as another example of the conventional example; FIG. 6 is a diagram illustrating the manufacturing method of another example of the conventional example. It is a diagram. 4... Polysilicon film, 5... Silicon oxide film, 6... Opening, 7... High melting point metal film, 8...・Low concentration diffusion layer, 9...Silicon oxide film, 9a...Side wall insulating film, 10...Gate electrode, 11...High concentration diffusion layer, 12...Source/drain diffusion layer. 1... Substrate, 3... Gate insulating film, Fig. ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Fig. ↓ ■ No. ↓ ↓ ↓ Fig. Manufacturing method of laser and other embodiments While explaining the above, Fig. 1 is a cross-sectional view showing the structure of another example of a conventional LDD structure transistor.

Claims (1)

[Claims] (1) A step of forming a gate insulating film (3) on the base film (1), and forming a first conductive film (4) on the gate insulating film (3). a step of depositing first and second conductive films (4) on the first conductive film (4);
, 7), forming a film (5) having an etching selectivity, selectively etching the film (5) having the etching selectivity to form an opening (6); forming a second conductive film (7) within the opening (6) by laser irradiation;
7), removing the film (5) having the etching selectivity, and using the second conductive film (7) as a mask to bury the underlying film (1).
) to form a low concentration diffusion layer (8) by introducing ions of the opposite conductivity type into the underlying film (1), and forming an insulating film ( 9), and etching back the insulating film (9) to form the second conductive film (9).
7) Forming a sidewall insulating film (9a) on the sidewall, and selectively forming the first conductive film (4) using the second conductive film (7) and the sidewall insulating film (9a) as a mask. etching the first and second conductive films (4, 7).
forming a gate electrode (10) consisting of the second conductive film (7) and the sidewall insulating film (9a) as masks, and applying ions of the opposite conductivity type to the underlying film (1) to the underlying film; is introduced into the film (1) to form a high concentration diffusion layer (11), thereby forming a source/drain diffusion layer (12) consisting of a low concentration diffusion layer (8) and a high concentration diffusion layer (11). A method for manufacturing a semiconductor device, comprising the steps of: (2) forming a gate insulating film (3) on the base film (1); forming a first conductive film (4) on the gate insulating film (3); The first and second conductive films (4) are disposed on the conductive film (4) of
, 7), forming a film (5) having an etching selectivity, selectively etching the film (5) having the etching selectivity to form an opening (6); forming a second conductive film (7) within the opening (6) by laser irradiation;
7), removing the film (5) having the etching selectivity, and using the second conductive film (7) as a mask to bury the underlying film (1).
) to form a low concentration diffusion layer (8) by introducing ions of the opposite conductivity type into the underlying film (1), and forming an insulating film ( 9), and etching back the insulating film (9) to form the second conductive film (9).
7) Forming a sidewall insulating film (9a) on the sidewall, and using the second conductive film (7) and the sidewall insulating film (9a) as a mask, ions of a conductivity type opposite to that of the underlying film (1) are formed. By introducing into the underlying film (1) to form a high concentration diffusion layer (11), a source/drain diffusion layer (12) consisting of a low concentration diffusion layer (8) and a high concentration diffusion layer (11) is formed. selectively etching the first conductive film (4) using the second conductive film (7) and the sidewall insulating film (9a) as a mask to form the first and second conductive films; conductive film (4, 7)
A method of manufacturing a semiconductor device, comprising the step of forming a gate electrode (10) consisting of: