JPH0442970A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0442970A JPH0442970A JP2148998A JP14899890A JPH0442970A JP H0442970 A JPH0442970 A JP H0442970A JP 2148998 A JP2148998 A JP 2148998A JP 14899890 A JP14899890 A JP 14899890A JP H0442970 A JPH0442970 A JP H0442970A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- pattern
- silicon film
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高集積および積層構造が容易な半導体装!お
よびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a semiconductor device that can be easily integrated and laminated! and its manufacturing method.
従来の技術
従来のMO3型半導体装置は第5図(A)に示すように
一導電型半導体基板40にゲート酸化膜41およびゲー
トを極42を形成し、このゲート電極42をマスクとし
て半導体基板40に不純物イオンを注入し、ソース・ド
レイン43.44を形成した後、第5図IB)に示すよ
うに、全面に絶縁膜45を形成し、さらに、選択的に開
孔部46.47.48を形成し、配線層49.50.5
1を形成していた。BACKGROUND OF THE INVENTION A conventional MO3 type semiconductor device, as shown in FIG. 5A, has a gate oxide film 41 and a gate electrode 42 formed on a semiconductor substrate 40 of one conductivity type, and uses this gate electrode 42 as a mask to form a gate oxide film 41 and a gate electrode 42 on the semiconductor substrate 40. After implanting impurity ions to form source/drains 43.44, an insulating film 45 is formed on the entire surface as shown in FIG. and wiring layer 49.50.5
It formed 1.
発明が解決しようとする課題
上述した従来のMO3型半導体装置では、半導体基板面
に対して、垂直方向にゲート酸化膜41、ゲート電極4
2、および配線層49.50.51を形成するため、パ
ターン寸法の微細化に対して、膜厚も薄膜化しないと、
開孔部46.47.48の縦と横の寸法比、いわゆるア
スペクト比が大きくなり、配線が断線しやすくなるとい
う欠点があった。また、ゲート電極や配線層の膜厚を薄
くすると抵抗が増加し、電気特性が劣化するという閉頭
があった。Problems to be Solved by the Invention In the conventional MO3 type semiconductor device described above, the gate oxide film 41 and the gate electrode 4 are formed in a direction perpendicular to the semiconductor substrate surface.
2, and wiring layers 49, 50, and 51, the film thickness must be made thinner as pattern dimensions become finer.
There was a drawback that the ratio of the vertical and horizontal dimensions of the openings 46, 47, and 48, so-called aspect ratio, became large, making the wiring more likely to break. Furthermore, when the thickness of the gate electrode or wiring layer is made thinner, the resistance increases and the electrical characteristics deteriorate.
本発明は上記問題を解決するもので、同一絶縁膜上に横
方向にゲート電極とソース・ドレイン領域およびチャネ
ル領域を形成して表面段差を少なくした半導体装置およ
びその製造方法を提供することを目的とするものである
。The present invention solves the above problem, and aims to provide a semiconductor device in which a gate electrode, a source/drain region, and a channel region are formed laterally on the same insulating film to reduce surface steps, and a method for manufacturing the same. That is.
課題を解決するための手段
上記問題を解決するために、本発明の半導体装置は、半
導体基板上に形成した絶縁膜上に、半導体結晶膜パター
ンを形成し、この半導体結晶膜パターンにソース・ドレ
インおよびチャネル領域を形成し、前記半導体結晶膜パ
ターンの側壁部にゲート酸化膜を介し隣接するゲート電
極を前記絶縁膜上に形成したものである。Means for Solving the Problems In order to solve the above problems, the semiconductor device of the present invention includes a semiconductor crystal film pattern formed on an insulating film formed on a semiconductor substrate, and a source/drain layer formed on the semiconductor crystal film pattern. and a channel region are formed, and a gate electrode adjacent to the side wall portion of the semiconductor crystal film pattern with a gate oxide film interposed therebetween is formed on the insulating film.
また、本発明の半導体装置の製造方法は、一導電型半導
体基板上に絶縁膜を形成する工程と、その上に多結晶硅
素膜を形成し、この多結晶硅素膜に所定の第1のパター
ンを形成してゲート電極を形成する工程と、前記ゲート
電極の側壁部にゲート酸化膜を形成する工程と、前記絶
縁膜に選択的に開孔部を形成し、さらに全面に単結晶硅
素膜を形成する工程と、前記開孔部を含む単結晶硅素膜
に前記多結晶膜パターンに一部が接した所定の第2のパ
ターンを形成する工程と、前記単結晶硅素膜よりなる第
2のパターンに選択的に不純物層を形成し、ソース・ド
レインを形成する工程を有する構成にしたものである。Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate of one conductivity type, forming a polycrystalline silicon film on the insulating film, and forming a predetermined first pattern on the polycrystalline silicon film. forming a gate electrode by forming a gate electrode, forming a gate oxide film on the sidewalls of the gate electrode, selectively forming an opening in the insulating film, and further forming a single crystal silicon film on the entire surface. forming a predetermined second pattern partially in contact with the polycrystalline film pattern on the single-crystal silicon film including the opening; and a second pattern made of the single-crystal silicon film. This structure includes a step of selectively forming an impurity layer on the semiconductor device and forming a source/drain.
さらに、本発明の製造方法は、一導電型半導体基板上に
絶縁膜を形成する工程と、前記絶縁膜に開孔部を形成し
、さらに全面に多結晶硅素膜を形成した後、単結晶化す
る工程と、前記開孔部を含む単結晶硅素膜に第1のパタ
ーンを形成した後、酸化して前記パターンの側壁にゲー
ト酸化膜を形成する工程と、前記第1のパターンと接す
る多結晶硅素膜よりなる第2のパターンを形成してゲー
ト電極を形成する工程と、前記単結晶硅素膜よりなる第
1のパターンに選択的に不純物イオンを注入し、ソース
・ドレインを形成する工程とを有する構成にしたもので
ある。Further, the manufacturing method of the present invention includes a step of forming an insulating film on a semiconductor substrate of one conductivity type, forming an opening in the insulating film, further forming a polycrystalline silicon film on the entire surface, and then forming a single crystal silicon film. forming a first pattern on the single crystal silicon film including the opening, and then oxidizing the single crystal silicon film to form a gate oxide film on the sidewalls of the pattern; a step of forming a second pattern made of a silicon film to form a gate electrode; and a step of selectively implanting impurity ions into the first pattern made of the single crystal silicon film to form a source/drain. The configuration is as follows.
作用
上記構成により、半導体基板上に形成した絶縁膜の同一
平面上に横方向に並列して、ゲート電極、ゲート酸化膜
とソース・ドレイン領域およびチャンネル領域を形成す
るため、従来例と興なり、ゲート電極およびソース・ド
レイン領域の高さを同一にすることができ、全面に薄い
絶縁膜を形成した後、前記すべての領域に同一の開孔部
を形成することが可能となり、また、下地の段差もない
ため、断線のしない微細配線を容易に形成すZ、ことが
できる。Operation With the above structure, the gate electrode, the gate oxide film, the source/drain region, and the channel region are formed laterally in parallel on the same plane of the insulating film formed on the semiconductor substrate. The height of the gate electrode and the source/drain regions can be made the same, and after forming a thin insulating film on the entire surface, it is possible to form the same opening in all the regions, and it is also possible to Since there is no difference in level, it is possible to easily form fine wiring without disconnection.
実施例 以下本発明の一実施例を図面にもとすいて説明する。Example An embodiment of the present invention will be described below with reference to the drawings.
第1図および第2図は本発明の第1の実施例の半導体装
1の製造方法を説明する断面図および上面図である。第
1図において、一導電型半導体基板1の上に二酸化硅素
膜などの絶縁膜2を形成し、その上に全面に第1の多結
晶硅素膜3を形成する(第1図(A) ) 、次に、第
1の多結晶硅素膜3に所定の第1のパターン4を形成し
てゲート電極とした後、第1のパターン4の多結晶硅素
膜を酸化し、ゲート酸化膜5を形成する(第1図(8)
)。1 and 2 are a sectional view and a top view illustrating a method of manufacturing a semiconductor device 1 according to a first embodiment of the present invention. In FIG. 1, an insulating film 2 such as a silicon dioxide film is formed on a semiconductor substrate 1 of one conductivity type, and a first polycrystalline silicon film 3 is formed on the entire surface (FIG. 1(A)). Next, a predetermined first pattern 4 is formed on the first polycrystalline silicon film 3 to form a gate electrode, and then the polycrystalline silicon film of the first pattern 4 is oxidized to form a gate oxide film 5. (Figure 1 (8)
).
次に、絶縁膜2の第1の多結晶硅素膜よりなる第1のパ
ターン4で覆われていない領域に開孔部6を形成l、た
後、全面に第2の多結晶硅素膜7を形成する(第1図(
C))。次に、l/−ザービーム等を第2の多結晶性@
膜7に照射1−て単結晶化した後、第1の多結晶硅素膜
よりなる第1のパターン4の側壁のデーl−酸化膜5に
整1−かつ開孔部6を覆う位置に第2のパターン8を形
成する(第1図(D))。Next, after forming an opening 6 in a region of the insulating film 2 that is not covered with the first pattern 4 made of the first polycrystalline silicon film, a second polycrystalline silicon film 7 is formed on the entire surface. form (Figure 1 (
C)). Next, the l/- laser beam etc. are applied to the second polycrystalline @
After the film 7 is irradiated to form a single crystal, a first pattern is applied to the sidewall of the first pattern 4 made of the first polycrystalline silicon film, and then the oxide film 5 is aligned with the oxide film 5 and at a position covering the opening 6. 2 patterns 8 are formed (FIG. 1(D)).
次に、第2図において、単結晶硅素膜よりなる第2のパ
ターン8およびゲート酸化膜5の一部の」−に感光性樹
脂膜9を形成j−た停、この感光性樹脂膜9をマスクと
して、第2のパターン8の単結晶硅素膜に不純物イオン
を注スL、ソース・ドレイン領域io、 ilを形成す
る(第2図([))。次に、感光性樹脂膜9を除去1.
た挾、全面に第2の絶縁膜12を形成し、選択的に開孔
$13.14.15を形成した後、金属配線M16.1
7.18を形成する(第2図(E))。、−れにより、
絶縁膜2の同一平面J−に、ゲートtiとソース・ドレ
イン領域およびチャンネル領域どを形成したMO5型半
導体装置が得られる。Next, in FIG. 2, a photosensitive resin film 9 is formed on a second pattern 8 made of a single crystal silicon film and a part of the gate oxide film 5. As a mask, impurity ions are poured into the single crystal silicon film of the second pattern 8 to form source/drain regions io and il (FIG. 2 ([)). Next, the photosensitive resin film 9 is removed 1.
Then, after forming the second insulating film 12 on the entire surface and selectively forming openings M13, 14, and 15, metal wiring M16.1 is formed.
7.18 (Figure 2 (E)). ,-by
An MO5 type semiconductor device is obtained in which a gate ti, a source/drain region, a channel region, etc. are formed on the same plane J- of the insulating film 2.
第3図および第4図はイi:発明の第2の実施例の半導
体装置の製造方法を説明する断面図および上面図である
、第3図においで、一導電梨半導体基板20の上に二酸
化硅素膜などの絶縁膜21を形成した後、絶縁膜21に
選択的に開孔部22を形成1.て半導体基板20を露出
させ、さらに、全面に多結晶硅素!123を形成i−た
後、レーザー光を照射1.て単結晶硅素膜に変換する(
第3図(八))。次に、前記単結晶硅素膜に開孔部22
を含む所定め第1のパターン24を形成した後、前記単
結晶膜よりなるパターン24にゲート酸化膜25を形成
する(第3図(B))。次に、多結晶硅素膜を全面に形
成しi: 擾、第1のパターン24の単結晶硅素膜の側
壁部に形成したゲート酸化膜25と接する第2のパター
ン26を形成してゲート電極とする(第3図fc))。3 and 4 are a cross-sectional view and a top view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the invention. After forming an insulating film 21 such as a silicon dioxide film, openings 22 are selectively formed in the insulating film 21.1. The semiconductor substrate 20 is exposed, and then the entire surface is covered with polycrystalline silicon! After forming 123, laser light is irradiated 1. to convert it into a single crystal silicon film (
Figure 3 (8)). Next, the opening 22 is formed in the single crystal silicon film.
After forming a predetermined first pattern 24 including a first pattern 24, a gate oxide film 25 is formed on the pattern 24 made of the single crystal film (FIG. 3(B)). Next, a polycrystalline silicon film is formed on the entire surface, and a second pattern 26 is formed in contact with the gate oxide film 25 formed on the side wall of the single crystal silicon film of the first pattern 24 to form a gate electrode. (Fig. 3 fc)).
次に、第4図において、単結晶硅素膜よりなる第1のパ
ターン24に第1の実施例の場合と同様に選択的に不純
物イオンを注入し、ソース・ドレイン領域27.28を
形成するく第4図(D))。次に全面に絶縁膜29を形
成し、選択的に開孔部30.31゜32を形成した後、
金属配線層33.34.35を形成する(第4図([)
)。これにより絶縁膜21の同一平面Fに、ゲートt’
にとソース・ドレイン領域およびチャンネル領域とを形
成したMO8型半導体装1が得られる。Next, in FIG. 4, impurity ions are selectively implanted into the first pattern 24 made of a single crystal silicon film to form source/drain regions 27 and 28, as in the first embodiment. Figure 4(D)). Next, after forming an insulating film 29 on the entire surface and selectively forming openings 30.31° 32,
Metal wiring layers 33, 34, 35 are formed (Fig. 4 ([)
). As a result, the gate t' is placed on the same plane F of the insulating film 21.
An MO8 type semiconductor device 1 having a source/drain region and a channel region is obtained.
発明の効果
以上のように、本発明によれば、同一絶縁膜上に横方向
にゲー■・電極、ゲー1へ酸化膜とソース・ドレイン領
域およびチャンネル領域を形成するため、配線層とゲー
1へ電極およびソース・トレインttiとの接続のため
の開孔部のアスベク1〜比が同一・となり、また表面段
差も少なく、断線の少ない配線層を容易に形成できる。Effects of the Invention As described above, according to the present invention, the wiring layer and the gate electrode are formed laterally on the same insulating film, the oxide film on the gate electrode, the source/drain region, and the channel region are formed on the gate electrode. The openings for connection with the electrode and the source train tti have the same aspic ratio of 1 to 1, and there are few surface steps, and a wiring layer with few disconnections can be easily formed.
また、表面も平坦であり、半導体装置を容易に$層構造
で形成することができる。Further, the surface is flat, and a semiconductor device can be easily formed in a $ layer structure.
第1図および第2図は本発明の第1の実施例の半導体装
置の製造方法を説明するための構造断面図および平面図
、第3図および第4図は本発明の第2の実施例の半導体
装置の製造方法を説明するための構造断面図および平面
図、第5図は従来例の半導体装置の製造方法を説明する
ための構造断面図である。
1.20・・・半導体基板、2.21・・・絶縁膜、4
.26・・・ゲート電極、5.25・・・デーl−酸化
膜、8,24・・・単結晶硅素膜パターン、10.11
.27.28・・・ソース・ドレイン領域。
代理人 森 本 義 弘
第2図
”−CN l’n マ り)1(心内第3F!!A1 and 2 are structural cross-sectional views and plan views for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. 3 and 4 are a structural cross-sectional view and a plan view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 5 is a structural cross-sectional view and a plan view for explaining a method of manufacturing a semiconductor device according to the prior art. FIG. 1.20...Semiconductor substrate, 2.21...Insulating film, 4
.. 26...Gate electrode, 5.25...Del-oxide film, 8,24...Single crystal silicon film pattern, 10.11
.. 27.28... Source/drain region. Agent Yoshihiro Morimoto 2nd floor - CN l'n Mari) 1 (3rd floor in the heart!!A)
Claims (1)
ゲート電極にゲート酸化膜を介して隣接する半導体結晶
膜を設け、この半導体結晶膜にソース・ドレイン領域お
よびチャネル領域を形成した半導体装置。 2、一導電型半導体基板上に絶縁膜を形成する工程と、
その上に多結晶硅素膜を形成し、この多結晶硅素膜に所
定の第1のパターンを形成してゲート電極を形成する工
程と、前記ゲート電極の側壁部にゲート酸化膜を形成す
る工程と、前記絶縁膜に選択的に開孔部を形成し、さら
に全面に単結晶硅素膜を形成する工程と、前記開孔部を
含む単結晶硅素膜に、前記多結晶膜パターンに一部が接
した所定の第2のパターンを形成する工程と、前記単結
晶硅素膜よりなる第2のパターンに選択的に不純物層を
形成し、ソース・ドレインを形成する工程を有する半導
体装置の製造方法。 3、一導電型半導体基板上に絶縁膜を形成する工程と、
前記絶縁膜に開孔部を形成し、さらに全面に多結晶硅素
膜を形成した後、単結晶化する工程と、前記開孔部を含
む単結晶硅素膜に第1のパターンを形成した後、酸化し
て前記パターンの側壁にゲート酸化膜を形成する工程と
、前記第1のパターンと接する多結晶硅素膜よりなる第
2のパターンを形成してゲート電極を形成する工程と、
前記単結晶硅素膜よりなる第1のパターンに選択的に不
純物イオンを注入し、ソース・ドレインを形成する工程
とを有する半導体装置の製造方法。[Claims] 1. A gate electrode and a semiconductor crystal film adjacent to the gate electrode via a gate oxide film are provided in parallel on the same plane of the insulating film, and a source/drain region and a semiconductor crystal film are provided in parallel on the same plane of the insulating film. A semiconductor device with a channel region formed. 2. Forming an insulating film on a semiconductor substrate of one conductivity type;
forming a polycrystalline silicon film thereon; forming a gate electrode by forming a predetermined first pattern on the polycrystalline silicon film; and forming a gate oxide film on the sidewalls of the gate electrode. , a step of selectively forming an opening in the insulating film and further forming a single crystal silicon film on the entire surface, and a part of the single crystal silicon film including the opening being in contact with the polycrystalline film pattern; A method for manufacturing a semiconductor device, comprising: forming a predetermined second pattern made of the single crystal silicon film, and selectively forming an impurity layer on the second pattern made of the single crystal silicon film to form a source/drain. 3. Forming an insulating film on a semiconductor substrate of one conductivity type;
After forming an opening in the insulating film and further forming a polycrystalline silicon film on the entire surface, a step of monocrystallizing the film, and forming a first pattern on the single crystal silicon film including the opening, oxidizing to form a gate oxide film on the sidewalls of the pattern; forming a second pattern made of a polycrystalline silicon film in contact with the first pattern to form a gate electrode;
A method for manufacturing a semiconductor device, comprising the step of selectively implanting impurity ions into the first pattern made of the single crystal silicon film to form sources and drains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2148998A JP2604487B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2148998A JP2604487B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0442970A true JPH0442970A (en) | 1992-02-13 |
| JP2604487B2 JP2604487B2 (en) | 1997-04-30 |
Family
ID=15465422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2148998A Expired - Fee Related JP2604487B2 (en) | 1990-06-06 | 1990-06-06 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2604487B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315143A (en) * | 1992-04-28 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | High density integrated semiconductor device |
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1990
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58132919A (en) * | 1982-02-03 | 1983-08-08 | Nec Corp | Manufacture of semiconductor device |
| JPS60160159A (en) * | 1984-01-05 | 1985-08-21 | ノーザン・テレコム・リミテッド | Mos device vertically integrated and method of producing same |
| JPS61242352A (en) * | 1985-04-19 | 1986-10-28 | Hitachi Ltd | optical disc |
| JPH02114670A (en) * | 1988-10-25 | 1990-04-26 | Seiko Epson Corp | field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315143A (en) * | 1992-04-28 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | High density integrated semiconductor device |
| US5409850A (en) * | 1992-04-28 | 1995-04-25 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing a high density semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2604487B2 (en) | 1997-04-30 |
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