JPH0443038U - - Google Patents
Info
- Publication number
- JPH0443038U JPH0443038U JP1990083105U JP8310590U JPH0443038U JP H0443038 U JPH0443038 U JP H0443038U JP 1990083105 U JP1990083105 U JP 1990083105U JP 8310590 U JP8310590 U JP 8310590U JP H0443038 U JPH0443038 U JP H0443038U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- timing circuit
- flop
- pager
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Mobile Radio Communication Systems (AREA)
- Transceivers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図乃至第３図はこの考案に係る送受信シス
テムのタイミング回路の実施例を示し、第１図は
回路図、第２図はタイミングチヤート、第３図は
論理回路の素子構成を変えた部分回路図。第４図
乃至第６図は従来例を示し、第４図は回路図、第
５図はページヤの出力データとデータストローブ
との関係を示すページヤ出力信号のタイミングチ
ヤート、第６図は第４図の回路図のタイミングチ
ヤートである。
主な符号の説明、１……ＮＯＲゲート、２，１
６……ＪＫフリツプフロツプ、３，１４……ＮＡ
ＮＤゲート、４，１５……インバータ、１２，１
３……Ｄタイプフリツプフロツプ。
Figures 1 to 3 show an embodiment of the timing circuit of the transmitting/receiving system according to this invention, with Figure 1 being a circuit diagram, Figure 2 being a timing chart, and Figure 3 being a portion of a logic circuit with a different element configuration. circuit diagram. 4 to 6 show conventional examples, FIG. 4 is a circuit diagram, FIG. 5 is a timing chart of a pager output signal showing the relationship between pager output data and data strobe, and FIG. This is a timing chart of the circuit diagram. Explanation of main symbols, 1...NOR gate, 2, 1
6...JK flip-flop, 3,14...NA
ND gate, 4, 15... Inverter, 12, 1
3...D type flip-flop.
Claims (1)
プフリツプフロツプと、ＯＲゲートと、ＮＡＮＤ
ゲートと、インバータと、ＪＫフリツプフロツプ
とで構成し、ページヤの出力データに伴うデータ
ストローブ信号によりスタートパルス信号を発生
させるタイミング回路において、 前記タイミング回路にＪＫフリツプフロツプと
、ＮＡＮＤゲートと、ＮＯＲゲートと、インバー
タとを設け、前記ページヤの出力データのタイミ
ングにスタートパルス信号を同期して出力させる
ように構成したことを特徴とする送受信システム
のタイミング回路。[Claims for Utility Model Registration] A D-type flip-flop, an OR gate, and a NAND transmitting/receiving system using a pager function.
In a timing circuit that includes a gate, an inverter, and a JK flip-flop, and generates a start pulse signal based on a data strobe signal accompanying output data of a pager, the timing circuit includes a JK flip-flop, a NAND gate, a NOR gate, and an inverter. A timing circuit for a transmitting/receiving system, characterized in that the timing circuit is configured to output a start pulse signal in synchronization with the timing of output data of the pager.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990083105U JPH0443038U (en) | 1990-08-07 | 1990-08-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990083105U JPH0443038U (en) | 1990-08-07 | 1990-08-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0443038U true JPH0443038U (en) | 1992-04-13 |
Family
ID=31630497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990083105U Pending JPH0443038U (en) | 1990-08-07 | 1990-08-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0443038U (en) |
-
1990
- 1990-08-07 JP JP1990083105U patent/JPH0443038U/ja active Pending
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