JPH0443309B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel digital signal processing circuit, and in particular, it can be used alone or in combination to produce digital filters, color encoders, matrix circuits, adders, and multipliers. The present invention aims to provide a new digital signal processing circuit that can configure various digital circuits such as the above.

Background technology and its problems Devices that make full use of advanced digital technology, such as digital color video cameras, include digital filters, matrix circuits, encoder circuits, etc.
Many types of digital circuits such as adders and multipliers are used. By the way, designing and manufacturing such various digital circuits individually leads to an extremely high cost of the device.

Purpose of the Invention The present invention provides a novel digital signal that can be used alone or in combination to construct various digital circuits such as digital filters, color encoders, matrix circuits, adders, and multipliers. It is intended to provide a processing circuit.

SUMMARY OF THE INVENTION The first digital signal processing circuit of the present invention to achieve the above object generates a product signal by multiplying signals of multiple bits by each other and delaying each multiple bits by a unit delay amount, the more significant the higher bit. a multiplier that outputs a multiplier, and an addition that adds the product signal output from the multiplier to a summand signal that is another multi-bit signal and is delayed by a unit delay amount for each multi-bit, the more significant the higher bit is. The semiconductor chip is characterized in that the parts and parts are formed on one semiconductor chip.

The second digital signal processing circuit of the present invention includes a multiplier that multiplies signals of multiple bits with each other and outputs a product signal delayed by a unit delay amount for each of the multiple bits, and the multiplier an adder for adding the product signal outputted from the addend signal to another multi-bit signal, which is delayed by a unit delay amount for each plurality of bits, the more significant the higher bit; The present invention is characterized in that an addend signal delay circuit that delays each bit of the sum signal by a unit delay amount is formed on one semiconductor chip.

The third digital signal processing circuit of the present invention includes a multiplier that multiplies signals of a plurality of bits with each other and outputs a product signal delayed by a unit delay amount for each plurality of bits, the higher the higher bit. A summand signal delay circuit that delays each bit of the summand signal by a unit delay amount, the higher the higher bit is delayed, and the output from the summand signal delay circuit. an adder that adds the product signal output from the multiplier to the summand signal; and a sum signal delay circuit that delays each bit of the sum signal output from the adder by a unit delay amount. and are formed on one semiconductor chip.

A fourth aspect of the digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplication section an adder for adding the product signal outputted from the addend signal to another multi-bit signal, which is delayed by a unit delay amount for each plurality of bits, the more significant the higher bit is; The amount of signal delay between each bit of the sum signal can be increased by applying a unit delay amount for each bit to the sum signal, which is delayed by a unit delay amount for each bit, the more the higher bit is delayed. a sum signal delay circuit that provides an equal amount of delay to each bit of the sum signal output from the adder;
A selector for receiving the output signals of two sum signal delay circuits and outputting one output signal designated by a select signal from among the output signals is formed on one semiconductor chip.

A fifth digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal delayed by a unit delay amount for each of the plurality of bits, and the multiplication section A signal in which the same signal as one of the multiplicand signal and the multiplier signal input to the multiplier signal is the upper bit and the same signal as the other is the lower bit, and the product signal output from the multiplier section are received and selected from among them. A selector that outputs one signal specified by a signal, and an addend that is a multi-bit signal different from the output signal of the selector and delayed by a unit delay amount for each plural bit, the higher the higher the bit. The present invention is characterized in that an adder for adding signals and an adder for adding signals are formed on one semiconductor chip.

A sixth aspect of the digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplication section Receives a signal in which the same signal as one of the multiplicand signal and multiplier signal input to the multiplicand signal is the upper bit and the same signal as the other is the lower bit, and calculates the unit delay for each multiple bits for the received signal. A delay circuit that provides a delay such that the delay amount increases as the more significant bits are received, a signal identical to the signal received by the delay circuit, an output signal of the delay circuit, and a product signal that is the output of the multiplier section A selector that outputs one signal specified by a select signal, and an addendum that converts the signal output from the selector into another multiple-bit signal, which is delayed by a unit delay amount for each multiple bits, the more significant the higher bit. The present invention is characterized in that an adding section for adding to a number signal is formed on one semiconductor chip.

A seventh digital signal processing circuit of the present invention includes a multiplier that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplier thereof. A variable delay circuit that provides an appropriate delay to both the input multiplicand signal and the multiplier signal or to the output signal of the multiplier, and a variable delay circuit that provides an appropriate delay to both the multiplicand signal and the multiplier signal input to the multiplier. a summand signal delay circuit that delays each bit of the summand signal by a unit delay amount; An adder for adding the product signals obtained by the adder, and a sum signal delay circuit for delaying each bit of the sum signal outputted from the adder by a unit delay amount, are formed on one semiconductor chip. It is characterized by:

The eighth digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits, and a multiplication section provided on the input side of the multiplicand signal and the multiplier signal or on the output side of the product signal. A delay circuit that delays a signal by a unit delay amount for each multiple bits, the more the higher bits are; a delay circuit that delays the summand signal by a unit delay amount for each multiple bits, the higher the higher bits; a delay circuit that delays the more significant bits by a unit delay amount for each bit, a delay circuit that delays the signal by the same delay amount as each bit of the summand signal, and two delay circuits that delay the summand signal. receive the output signal,
A first selector that outputs the output signal specified by the first select signal, and a product signal that is delayed by a unit delay amount for each plurality of bits from the multiplier, and the more significant the higher bit is, the more delayed the product signal is from the first selector. an adder that adds to the output summand signal, a delay circuit that delays the sum signal output from the adder by the same amount of delay for each bit, and a delay circuit that adds the sum signal output from the adder to multiple bits. Receives the output signals of the above two delay circuits, one that delays the lower bit by a unit delay amount for each signal, and the other that delays the sum signal, and outputs the output signal of the one of the delay circuits specified by the second select signal. A second selector for outputting the output signal is formed on one semiconductor chip.

These digital signal processing circuits of the present invention can be used alone or in combination to construct various digital circuits.

Embodiments Below, the digital signal processing circuit of the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 1 shows a first embodiment of a digital signal processing circuit according to the present invention. In the same figure, 2,
Delay circuits 3 and 4 are connected in series to each other and delay the n-bit multiplicand signal A by a unit delay amount, and 5 receives the output signals of the delay circuits 2, 3, and 4 and selects one of the output signals. This is a selector that sends out one output signal specified by the signal. Delay circuits 6, 7, and 8 are connected in series and each delays the n-bit multiplier signal B by a unit delay amount; 9 receives the output signals of the delay circuits 6, 7, and 8; This is a selector that sends out one output signal specified by a select signal. These 2, 3, 4, 5 and 6,
7, 8, and 9 constitute variable delay circuits 10 and 11, respectively, which delay each bit of the signals A and B by an appropriate delay amount. Thus, the input multiplicand signal A and multiplier signal B can be delayed by one to three times the unit delay amount by the select signals that control the selectors 5 and 9. Note that instead of inserting the variable delay circuits 10 and 11 into both the multiplicand signal and the multiplier signal, the multiplier 1
It is also possible to insert a delay circuit 10' (indicated by a broken line in FIG. 1) having a long word length on the output side of the circuit 7.

12 is a delay circuit which accepts the multiplier signal B as the lower bit signal, receives the multiplicand signal A as the upper bit signal, and outputs the multiplicand signal A and the multiplier signal B.
It functions to delay a single 2n-bit signal consisting of For example, this delay circuit 12 has a configuration as shown in FIG. Alternatively, the delay amount may be increased by a unit delay amount for every 4 bits, the higher the signal is. The reason why a multi-bit digital signal is delayed as the more significant bits are delayed is so that the multiplication section and addition section, which will be described later, can be formed by low-speed logic elements.

That is, in digital color video camera circuits and the like, it is generally necessary to use a very high-speed logic element such as TTL or ECL in an arithmetic unit that adds or multiplies data of multiple bits, for example 8 bits. This is because when adding multiple bits of signals, generally the lowest order bits are first calculated, and then the presence or absence of a carry is determined, and then the lower order bits are calculated. After the bit operation is completed, it is necessary to proceed to the operation on the upper bits, and calculating all bits simultaneously requires a large propagation delay time and requires a high-speed logic element. Figure 3a
is such an 8-bit ripple carry adder circuit. 13 is a 1-bit flip-flop, 1
4 is a 1-bit full adder. Of course, all bits can be computed at high speed by using an arithmetic unit with a carrier pullhead circuit, but in this case, a carrier pullhead circuit must be provided, and the operating speed is still at a carrier speed. The propagation speed is limited to Therefore, using a delay circuit as shown in Fig. 3b, the addition input is set to have a unit delay for each bit, with the delay increasing as the higher order bits go. The processing is performed at a processing speed of 1 bit per period of the clock pulse, while the processing is performed at a processing speed of 1 bit per period of the clock pulse.On the other hand, the processing speed is Using a delay circuit as shown in Figure 3c, a delay is applied to each bit by a unit delay, with the delay increasing for the lower bits, so that the signals of all bits of data originally at the same time are output at the same time. It is possible to do so. This is because the arithmetic unit can perform calculations on data at the same time at a very low processing speed of 1 bit per period of the clock pulse. However, in this case, the number of delay elements 13 of the delay circuit provided on the input side and the output side of the arithmetic unit must be greatly increased. By the way, according to the example shown in Fig. 3b and c, each delay circuit has 28 delay elements 13.
must be used, the required number of delay elements 13 becomes a non-negligible number.

The arithmetic unit of the digital signal processing circuit of the present invention uses a plurality of bits, for example, a 2-bit full addition block shown in FIG. 4, as a unit of the arithmetic unit. In this way, an arithmetic circuit having a 2-bit full addition block as a unit of arithmetic unit has a circuit configuration as shown in FIG. According to such an arithmetic circuit, flip-flops 13 and 1 shown at 15 and 16
Although this requires a delay circuit consisting of 3, . . . , the operating speed is faster than that of the arithmetic unit shown in FIG. Then, when performing calculations by delaying the signal to be operated by a unit delay amount for each bit so that the more significant the bit, the larger the delay amount, Figure 3 b and c are necessary.
The delay circuit (for example, 15, 16) according to the present invention requires fewer delay elements such as the flip-flop 13 than the delay circuit shown in FIG. That is, according to the present invention, speeding up can be achieved without unnecessarily increasing the number of delay elements in the delay circuit. Of course, the number of bits of the full addition block, which is the unit of the arithmetic unit, is not limited to the 2, 4, etc. mentioned as examples. The number of bits in this arithmetic block is determined by the fact that the propagation delay time required to output the carry of a 1-bit full adder is generally faster than the propagation delay time required to output the addition result of a 1-bit full adder. It is best to choose the number of bits so that they are about the same.

By doing so, the digital signal processing circuit 1 can be constructed from low-speed logic elements such as complementary MOS.

In any case, since such an arithmetic unit is used, a delay circuit such as No. 15 is required on the input side of the arithmetic unit, in which the delay amount is larger for higher-order bits. That is,
As the delay circuit 12 shown in FIG. 1, the circuit shown in FIG. 2 a or b is required when the number of bits in the block of the arithmetic unit is 2 or 4, respectively.
In the drawings, the difference in delay depending on the bit is expressed by showing the output side or input side of the block frame showing the circuit with a diagonal line.

A multiplier 17 multiplies the multiplicand signal A and the multiplier signal B output from the selectors 5 and 9 by each other. This multiplication section 17 has an adder circuit as shown in FIG. 5 as a basic element, and as a result of multiplication, an output of 2n-1 bits is obtained in a two's complement code. However, all of the many adder circuits that make up this multiplier section require input data with a longer delay for the higher-order bits, so delay circuits like 15 and 16 are not necessary for each adder circuit, but are used at the input portion of the multiplier section. and is only needed in the output part. Furthermore, since there is an adder section to be described later in the subsequent stage, a delay circuit such as 16 is not required in the output section.For example, if the multiplier section 17 outputs data with a unit delay amount for every 2 bits, the higher the bit, the larger the delay amount. good.

18 is a selector, which receives a signal consisting of the product signals A and B output from the multiplier 17, the multiplicand signal A and the multiplier signal B output from the selectors 5 and 9;
It receives the signals consisting of the multiplicand signal A and the multiplier signal B output from the delay circuit 12, and sends out the signal designated by the select signal from among these signals.

The path passing through the delay circuit 12 is for bypassing the multiplier 17 and operating the digital signal processing circuit 1 as an adder, and has the role of supplying a signal with a predetermined delay to the adder 22, which will be described later. accomplish Also, directly from selectors 5 and 9 to selector 1
The path for transmitting the signal to 8 is for the same purpose when a signal is input to inputs A and B, the more significant the delay of which is the higher the bit.

19 is a delay circuit that delays each bit of the 2n-1+α-bit augend signal C by an equal unit delay amount, and 20 is a delay circuit that delays the augend signal C by a unit of a plurality of bits (for example, every 2 (or 4, etc.) bits as the higher bits go). This is a delay circuit that delays the signal so that the amount of delay increases by the amount of delay, and its configuration is the same as that of the delay circuit 12, except that each bit is delayed by one stage more and the number of bits is different. A selector 21 receives the output signal of the delay circuit 19 and the output signal of the delay circuit 20, and outputs an output signal designated by the select signal from among them. Note that the path passing through the delay circuit 20 is for providing the summand signal C to an adder 22, which will be described later, as a signal having a predetermined amount of delay. Furthermore, the path passing through the delay circuit 19 is for when a signal is input as the summand signal C, the more significant the delay of which is the higher the bit.

Reference numeral 22 denotes an adder that adds the signal output from the selector 18 to the summand signal C output from the selector 21. As already explained, it has a structure in which the calculation is performed on multiple bits, for example, 2 bits at a time, the higher the higher the bit, the later the time is. It's summery. 23 is a sum signal delay circuit that delays each bit of the sum signal output from the adder 22 by a unit delay amount; 24 is a sum signal delay circuit that delays the sum signal output from the adder 22 so that the delay amount becomes larger for the lower bits. This is a delay circuit that allows This delay circuit 24 delays the signal output from the adder 22 by, for example, 2 bits in order from the lower bit to the upper bit every time a unit delay time elapses, so that the lower bits are delayed longer. This is to ensure that all bit signals that were originally sampled at the same time before being input to the circuit are output at the same time. This corresponds to the delay circuit 16 shown in FIG. 2, and each bit is delayed by one stage more than the circuit shown in FIG.

A selector 25 receives the output signals of the sum signal delay circuit 23 and the sum signal delay circuit 24 and sends out an output signal D specified by the select signal. Here, the path 23 is for outputting the signal of the adder 22, which is delayed by a unit delay amount every two bits, the more significant the higher bit is, in its delayed form. The path 24 is for correcting the delay of the signal, which differs depending on the bit, and outputting the signal D in a form in which the normal delay amount for each bit is the same.

The digital signal processing circuit 1 shown in FIG. 1 is configured as a one-chip IC.
The functions exhibited by the digital signal processing circuits can be changed depending on the control content by the select signals of each selector 5, 9, 18, 21, and 25.

6a to 6i show some examples of circuits that can be obtained by changing the select signals applied to each selector 5, 9, 18, 21, and 25 of the digital signal processing circuit 1. In the figure, 1a to 1i indicate substantial circuits of the digital signal processing circuit 1 in each state. 1 shown in Figure 6a
a indicates that the digital signal processing circuit 1 is in the following state, that is, the selectors 5 and 9 send out the outputs of the delay circuits 2 and 6, the selector 18 sends out the output of the multiplier 17, and the selector 21 sends out the output of the delay circuit 20. This is a circuit obtained by sending out A.
Perform the calculation B+C. However, if the input side of the delay circuit 20 is grounded or the like and the summand signal C is set to "0", it functions as a multiplication circuit that multiplies A and B.

In 1b shown in FIG. 6b, selectors 5 and 9 send out the outputs of delay circuits 2 and 6, selector 18 sends out the output of delay circuit 12, selector 21 sends out the output of delay circuit 20, and 25 is an adder circuit obtained by sending out the output of the delay circuit 24. This adder circuit 1b is an adder circuit that adds C to a signal AB whose upper bits are A and whose lower bits are B (herein, A×B is not meant). In this way, each selector 5, 9, 1
Although the substantial circuit configuration of the digital signal processing circuit 1 can be changed by appropriately controlling the selectors 8, 21, and 25 using respective select signals, in the following description of the circuits 1c to 1i, each selector 5,
For the sake of convenience, descriptions of the selection states 9, 18, 21, and 25 will be omitted.

1c shown in FIG. 6c is a product-sum circuit constituting the FIR digital filter, 1d shown in the same figure d is an adder circuit, and FIG. 7a is a product-sum circuit 1c ₄ , 1c ₃ , 1
A 5-tap FIR digital filter consisting of c ₂ , 1c ₁ , 1c ₀ and an adder circuit 1d is shown, and FIG. 7b is an equivalent circuit diagram thereof. Specifically, this FIR digital filter has an input signal X as a multiplicand signal A to each of the five product-sum circuits 1c that constitute it.
is applied, and a constant signal h ₄ ,
h ₃ , h ₂ , h ₁ , h ₀ are applied to the product-sum circuit 1c ₄ , 1 which also receives h ₄ , h ₃ as the multiplier signal B.
The input sides of the delay circuits 19, ₁₉ of c3 are grounded, and the summand signal C thereof is set to 0. Therefore, the product-sum circuits 1c ₄ and 1c ₃ are substantially h ₄ ·X and h ₃ ·
It functions only as a multiplication circuit to obtain X.

The output signal of the product-sum circuit 1c ₄ is a constant signal h _2
The output signal D of this product-sum circuit _1c2 is input as the summand signal C to the product-sum circuit _1c2 that receives the constant signal _h0 . . Further, the output signal D of the product-sum circuit _1c3 is sent to the summand signal C to the product-sum circuit _1c1 which receives the constant signal _h1 .
is entered as . The output signal of the product-sum circuit _1c0 is input as an addend signal C to the adder circuit 1d shown in FIG. 6d, and the output signal of the product-sum circuit _1c1 is input as an addend signal to the adder circuit 1d. be done. As for the output signal of this product-sum circuit _1c1 , the signal U of the upper bit is inputted to the delay circuit 2 as if it were the multiplicand signal A, and the signal L of the lower bit is inputted to the delay circuit 6 as if it were the multiplier signal B. However, since the signals A and B do not go through the multiplier 17, they are not multiplied.

The circuit shown in FIG. 7a is a product-sum circuit 1c ₄ , 1
Instead of connecting c ₃ , 1c ₂ , 1c ₁ , and 1c ₀ in cascade, there is a circuit in which 1c ₄ , 1c ₂ , and 1c ₀ are connected in cascade, and a circuit in which 1c ₃ and 1c ₁ are connected in cascade. , and the output signals of the two circuits are added together by an adder circuit 1d.

This is because each product-sum circuit 1c not only has a delay circuit 23 on the output side of the adder 22, but also has a delay circuit 19 on the addend signal input side of the adder 22. If all product-sum circuits 1c ₄ ~ 1
When c ₀ are connected in series, each product signal h ₄・
Compared to _the delay amount of X, h ₃ · X, h ₂ · X, h ₁ · This is because there will be an additional delay due to the amount of delay, and predetermined filter characteristics will no longer be obtained. Note that between the output signal of the product-sum circuit 1c ₀ and the output signal of the product-sum circuit 1c ₁ , the latter must be delayed by a larger unit delay amount, so the adder circuit 1
d, on the one hand, the output signal of the product-sum circuit 1c ₀ is delayed by a unit delay amount by the delay circuit 19, and on the other hand, the output signal of the product-sum circuit 1c ₁ is delayed by delay circuits 2, 3,
6 and 7, the delay is delayed by twice the unit delay amount.
Furthermore, the adder 22 that adds the two output signals outputs a 2n-1+α (α is a positive integer) bit digital signal in order from the lower bit.
The delay circuit 24 causes signals of lower bits to be delayed by, for example, a unit delay amount every two bits, so that signals of all bits of samples originally at the same time are output at the same time.

If a digital filter is configured in this way, N+1 digital signal processing circuits 1
By setting N of them to the mode of a product-sum circuit 1c as shown in FIG. 6c, and using the remaining one in the mode of an adder circuit 1d as shown in FIG. 6d. An N-tap FIR digital filter, which is widely used in video cameras and other devices, can be obtained.

1e shown in FIG. 6e is a multiplier 17 that delays the multiplier signal A and the multiplicand signal B by three times the unit delay
A product-sum circuit configured to input
f is an adder circuit that adds together a signal in which the upper bit side signal is A and the lower bit side signal is B and the summand signal C, and takes out the sum signal via the delay circuit 24. be. The product-sum circuit 1e, the adder circuit 1f, and the product-sum circuit 1c constitute an inner product circuit as shown in FIG.

This inner product circuit is a product-sum circuit 1 that calculates X ₀ and Y ₀ .
c ₁ , a product-sum circuit 1e ₁ that adds X ₁・Y ₁ to the output of the product-sum circuit 1c ₁ , and a product-sum circuit 1c ₂ that calculates X ₂・Y ₂ .
, a product-sum circuit 1e ₂ that adds X ₃ and Y ₃ to the output of the product-sum circuit 1c 2 , and a product-sum circuit 1e ₂ that adds X 3 and Y 3 to the output of the product-sum circuit 1e ₁ and the product-sum circuit 1
This includes an adder circuit 1f that adds the output of _e2 . According to this inner product circuit, X ₀・Y ₀ +X ₁・Y ₁ +
It is possible to perform _{the fourth-order inner product calculation of X 2 ·} Y _{2 +} It is ideal for performing matrix operations. For example, matrix operations such as Y I Q = a ₁₁ a ₁₂ a ₁₃ a ₂₁ a ₂₂ a ₂₃ a ₃₁ a ₃₂ a ₃₃ R G B are as follows: Y = a ₁₁・R+a ₁₂・G+a ₁₃・B I=a ₂₁・R+a ₂₂・G+a ₂₃・B Q a ₃₁・R+a ₃₂・G+a ₃₃・B, which is against such a cubic inner product operation. In this inner product circuit, the product-sum circuit 1e ₂ that receives X ₁ , Y ₁ and X ₃ , Y ₃ multiplies more than the product-sum circuit 1c ₁ , 1c ₂ that receives X ₀ , Y ₀ and X ₂ , Y ₂ . The delay amount of the vector signals
It is made to be twice as large. This is a product-sum circuit 1c that includes all four product-sum circuits as shown in Figure 6c.
_{When configured by _ _ _ _ _} This is because it will be done.

When the inner product circuit is constructed in this manner, a circuit capable of performing inner product calculations between L-dimensional vectors X and Y can be obtained using approximately 1.5L-0.5 digital signal processing circuits 1.

FIG. 6g shows a product-sum circuit 1g that utilizes a delay circuit 24 in place of the delay circuit 23 of the product-sum circuit 1e, and ends up as an inner product circuit that performs an inner product operation between two-dimensional vectors X and Y. It is unsuitable for use as a stage. FIG. 9 shows an inner product circuit using the delay circuit 1g. This inner product circuit inputs the output signal X ₀ · Y ₀ of the delay circuit 1c to the product-sum circuit 1g as an addend signal C, and from the delay circuit 24 of the product-sum circuit 1g, X ₀ ·Y ₀ +X ₁ ·Y ₁ It becomes like getting.

In this way, if the product-sum circuits 1c and 1g are used, 2
An inner product circuit for calculating the inner product of dimensional vectors X and Y can be configured by only two digital signal processing circuits 1. Such two-dimensional inner product circuits are quadrature modulation circuits used in video cameras, etc.
Alternatively, it can be used in a keying (crossfade) circuit.

Fig. 6h shows an adder circuit 1h suitable for the input stage of the adder tree circuit, Fig. 6i shows an adder circuit 1i also suitable for the intermediate stage, and Fig. 10 shows the adder circuit 1h.
An adder tree circuit using h, 1i and the adder circuit 1f is shown.

This adder tree circuit has input signals X ₀ ~ X ₃ and Y ₀
Four adder circuits 1h ₁ , 1h ₂ , 1h ₃ , 1h ₄ that add _the corresponding values of ~Y ₃ to each other are used as _input stages;
The output signals of the adder circuit 1i ₁ which adds together the output signals of X ₀ +Y ₀ and X ₁ +Y ₁ , and the output signals of the adder circuits 1h ₃ and 1h ₄ , i.e., X ₂ +Y ₂ and X ₃ +Y ₃ . An adder circuit 1i ₂ that adds together is used as an intermediate stage. The output stage contains the output signals of adder circuits 1i ₁ and 1i ₂ , that is, X ₀ +Y ₀ +X ₁ +Y ₁ and X ₂ +Y ₂ +
The aforementioned addition circuit 1f that adds X ₃ + Y ₃ to each other
is used.

In this way, the digital signal processing circuit 1 shown in FIG.
By appropriately selecting the type of signal to be sent according to the designation by the select signal, it is possible to change the substantial circuit configuration and perform different functions, as shown in FIG. 6 a to i, for example. . Therefore, digital filters, color encoders,
Many types of digital circuits such as matrices, adders, multipliers, etc. can be constructed by one digital signal processing circuit or by combining a plurality of digital signal processing circuits.

The digital signal processing circuit shown in FIG. 1 is merely an embodiment of the present invention, and 1a to 1i shown in FIGS. These are only some examples of circuits that can be obtained by controlling the circuit. For example, the variable delay circuit 10 in FIG.
The signals A and B input to 11 are all sent to selector 18.
Since the signal passes through the path between the selector 18 and the adder 22, a variable delay circuit with an appropriate bit length is provided between the selector 18 and the adder 22 instead of the variable delay circuits 10 and 11.
You can have the same functionality by adding one. Furthermore, various variations can be considered for each section depending on how the number of bits is determined in the calculation blocks of the multiplication section and the addition section.

Effects As described above, the first digital signal processing circuit of the present invention multiplies signals of multiple bits with each other, and generates a product signal in which the higher bits are delayed by a unit delay amount for each multiple bits. A multiplier for outputting the multiplier, and an adder for adding the product signal output from the multiplier to another multi-bit signal, which is delayed by a unit delay amount for each plurality of bits, the higher the higher the bit. and are formed on one semiconductor chip.

The second digital signal processing circuit of the present invention includes a multiplier that multiplies signals of multiple bits with each other and outputs a product signal delayed by a unit delay amount for each of the multiple bits, and the multiplier an adder for adding the product signal outputted from the addend signal to another multi-bit signal which is delayed by a unit delay amount for each plurality of bits, the more significant the higher bit; and an addend signal delay circuit which delays each bit of the sum signal by a unit delay amount, and is formed on one semiconductor chip.

The third digital signal processing circuit of the present invention includes a multiplier that multiplies signals of a plurality of bits with each other and outputs a product signal delayed by a unit delay amount for each plurality of bits, the higher the higher bit. A summand signal delay circuit that delays each bit of the summand signal by a unit delay amount, the higher the higher bit is delayed, and the output from the summand signal delay circuit. an adder that adds the product signal output from the multiplier to the summand signal; and a sum signal delay circuit that delays each bit of the sum signal output from the adder by a unit delay amount. and are formed on one semiconductor chip.

A fourth aspect of the digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplication section an adder for adding the product signal outputted from the addend signal to another multi-bit signal which is delayed by a unit delay amount for each plurality of bits, the more significant the higher bit; The signal delay between each bit of the sum signal is increased by applying a unit delay amount to each multiple bits, which is delayed more to the lower bits by a unit delay amount to each of the multiple bits. A sum signal delay circuit that eliminates the difference in amount, a sum signal delay circuit that delays each bit of the sum signal output from the adder by an equal amount of delay, and the two sum signal delay circuits. A selector for receiving output signals and outputting one output signal designated by a select signal from among the output signals is formed on one semiconductor chip.

A fifth digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal delayed by a unit delay amount for each of the plurality of bits, and the multiplication section A signal in which the same signal as one of the multiplicand signal and the multiplier signal input to the multiplier signal is the upper bit and the same signal as the other is the lower bit, and the product signal output from the multiplier section are received and selected from among them. A selector that outputs one signal specified by a signal, and an addend that is a multi-bit signal different from the output signal of the selector and delayed by a unit delay amount for each plural bit, the higher the higher the bit. The present invention is characterized in that an adder for adding signals and an adder for adding signals are formed on one semiconductor chip.

A sixth aspect of the digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplication section Receives a signal in which the same signal as one of the multiplicand signal and multiplier signal input to the multiplicand signal is the upper bit and the same signal as the other is the lower bit, and calculates the unit delay for each multiple bits for the received signal. A delay circuit that provides a delay such that the delay amount increases as the more significant bits are received, a signal identical to the signal received by the delay circuit, an output signal of the delay circuit, and a product signal that is the output of the multiplier section A selector that outputs one signal specified by a select signal, and an addendum that converts the signal output from the selector into another multiple-bit signal, which is delayed by a unit delay amount for each multiple bits, the more significant the higher bit. The present invention is characterized in that an adding section for adding to a number signal is formed on one semiconductor chip.

A seventh digital signal processing circuit of the present invention includes a multiplier that multiplies signals of a plurality of bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the plurality of bits, and the multiplier thereof. A variable delay circuit that provides an appropriate delay to both the input multiplicand signal and the multiplier signal or to the output signal of the multiplier, and a variable delay circuit that provides an appropriate delay to both the multiplicand signal and the multiplier signal input to the multiplier. a summand signal delay circuit that delays each bit of the summand signal by a unit delay amount; An adder for adding the product signals obtained by the adder, and a sum signal delay circuit for delaying each bit of the sum signal outputted from the adder by a unit delay amount, are formed on one semiconductor chip. It is characterized by:

The eighth digital signal processing circuit of the present invention includes a multiplication section that multiplies signals of a plurality of bits, and a multiplication section provided on the input side of the multiplicand signal and the multiplier signal or on the output side of the product signal. A delay circuit that delays a signal by a unit delay amount for each multiple bits, the more the higher bits are; a delay circuit that delays the summand signal by a unit delay amount for each multiple bits, the higher the higher bits; a delay circuit that delays the more significant bits by a unit delay amount for each bit, a delay circuit that delays the signal by the same delay amount as each bit of the summand signal, and two delay circuits that delay the summand signal. receive the output signal,
A first selector that outputs the output signal specified by the first select signal, and a product signal that is delayed by a unit delay amount for each plurality of bits from the multiplier, and the more significant the higher bit is, the more delayed the product signal is from the first selector. an adder that adds to the output summand signal, a delay circuit that delays the sum signal output from the adder by the same amount of delay for each bit, and a delay circuit that adds the sum signal output from the adder to multiple bits. Receives the output signals of the above two delay circuits, one that delays the lower bit by a unit delay amount for each signal, and the other that delays the sum signal, and outputs the output signal of the one of the delay circuits specified by the second select signal. A second selector for outputting the output signal is formed on one semiconductor chip.

Various digital circuits can be constructed by using these elements alone or in appropriate combinations. Therefore, according to the present invention, it is possible to eliminate the need to individually design and manufacture various digital circuits, and the cost of the device can be reduced.

Furthermore, the signal to be operated on is delayed by a unit delay amount for each multiple bits, the higher the bit, the higher the bit, so that the signal of multiple bits that is sequentially output every time the unit delay time elapses can be processed as a processing unit, thereby increasing the processing speed. The number of delay elements required for a delay circuit that can increase the speed and also delay the more significant bits of a signal, or eliminate the delay relationship between bits of a signal where the more significant bits are delayed. As mentioned above, there is no need to increase the number unnecessarily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the digital signal processing circuit of the present invention, FIGS. Figure a is a block diagram showing a general adder circuit, Figures b and c are block diagrams showing a delay circuit that is required when processing a signal in which each bit is delayed by a unit delay amount, the more significant the higher bit is. The figure is a block diagram showing a 2-bit full addition block that constitutes the arithmetic circuit of a digital signal processing circuit, and FIG. 5 shows the configuration of an example of an arithmetic unit in which the full addition block shown in FIG. 6A to 6I are block diagrams showing the substantial circuit configuration in each state of the digital signal processing circuit, and FIGS. 7A and 7B are block diagrams showing the configuration of the digital signal processing circuit in which a plurality of digital signal processing circuits of the present invention are combined. An example of a digital filter constructed in this way is shown, and a is a block diagram showing the circuit configuration;
b is an equivalent circuit diagram thereof, and FIGS. 8 to 10 are block diagrams showing other examples of digital circuits constructed by combining a plurality of digital signal processing circuits of the present invention. Explanation of symbols, 1...Digital signal processing circuit,
12... Delay circuit, 17... Multiplier, 18... Selector, 19, 20... Addend signal delay circuit, 2
2...Addition unit, 23...Sum signal delay circuit, 24...
...Sum signal delay circuit, 25...Selector.

Claims (1)

[Scope of Claims] 1. A multiplier that multiplies signals of multiple bits with each other and outputs a product signal that is delayed by a unit delay amount for each of the multiple bits, the more significant the higher bit is, and the product signal output from the multiplier. and an adder section for adding the summand signal, which is another multi-bit signal and is delayed by a unit delay amount for each plurality of bits, the higher the higher bits, the more the addend signal is formed in one semiconductor chip. Digital signal processing circuit. 2. A multiplier that multiplies signals of multiple bits together and outputs a product signal that is delayed by a unit delay amount for each multiple bits, the higher the higher bit. An adder section that adds a signal to the summand signal, which is delayed by a unit delay amount for each plurality of bits, the higher the higher the bit, and a unit delay for each bit of the sum signal output from the adder section. What is claimed is: 1. A digital signal processing circuit comprising: a summand signal delay circuit that provides a delay of a certain amount; 3. A multiplier that multiplies signals of multiple bits with each other and outputs a product signal in which the higher bits are delayed by a unit delay amount for each multiple bits, and the higher bits are delayed by a unit delay amount for each multiple bits. an addend signal delay circuit that delays each bit of the summand signal by a unit delay amount; A sum signal delay circuit that provides a delay of a unit delay amount to each bit of the sum signal output from the adder is formed on one semiconductor chip. A digital signal processing circuit characterized by: 4. A multiplier that multiplies signals of multiple bits with each other and outputs a product signal that is delayed by a unit delay amount for each multiple bits, the higher the higher bit. an adder that adds to the summand signal, which is a signal that is delayed by a unit delay amount for each plurality of bits, the more the higher bit is delayed; and an addend signal that is output from the adder and is delayed by a unit delay amount for each multiple bits, the more the upper bit is delayed. A sum signal delay circuit that eliminates the difference in the signal delay amount between each bit of the sum signal by applying a unit delay amount to each plurality of bits, the more delay the lower bits have, to the sum signal, and the above-mentioned addition. a sum signal delay circuit that delays each bit of the sum signal outputted from the sum signal by an equal amount of delay;
A digital signal processing circuit comprising: a selector for receiving output signals of two sum signal delay circuits and outputting one output signal specified by a select signal from among the output signals, formed on one semiconductor chip. 5. A multiplier that multiplies signals of multiple bits with each other and outputs a product signal delayed by a unit delay amount for each multiple bits, the higher the higher bit, and the multiplicand signal and multiplier signal input to the multiplier. A selector that receives the same signal as one of the signals as the upper bit and the same signal as the other as the lower bit and the product signal output from the multiplier and outputs one signal specified by the select signal from among the signals. and an adder for adding the output signal of the selector to the summand signal, which is a separate multi-bit signal and is delayed by a unit delay amount for each plural bits, the higher the higher bits, the addend signal is integrated into one semiconductor. A digital signal processing circuit characterized by being formed on a chip. 6 A multiplier that multiplies signals of multiple bits with each other and outputs a product signal delayed by a unit delay amount for each multiple bits, the more significant the higher bit is. A signal with the same signal as one as the upper bit and the same signal as the other as the lower bit is received, and the received signal is delayed by a unit delay for each multiple bits, with the higher the bit, the greater the delay. a delay circuit that receives a signal identical to the signal received by the delay circuit, an output signal of the delay circuit, and a product signal that is the output of the multiplication section, and outputs one signal specified by the select signal from among them. A selector and an adder that adds the signal output from the selector to another multi-bit signal, which is delayed by a unit delay amount for each plurality of bits, the higher the higher bit, the more the summand signal. A digital signal processing circuit characterized by being formed on a semiconductor chip. 7. A multiplier that multiplies signals of multiple bits with each other and outputs a product signal that is delayed by a unit delay amount for each multiple bits, the higher the higher bit, and both the multiplicand signal and the multiplier signal input to the multiplier. Alternatively, a variable delay circuit that gives an appropriate delay to the output signal of the multiplier, and a signal of each bit of the summand signal, which is a multi-bit signal and is delayed by a unit delay amount for each plurality of bits, the more significant the higher bit. an addend signal delay circuit that delays the summand signal by a unit delay amount; an addition section that adds the product signal output from the multiplication section to the summand signal output from the summand signal delay circuit; A digital signal processing circuit comprising: a sum signal delay circuit that delays each bit of the sum signal outputted from an adder by a unit delay amount; and a sum signal delay circuit that is formed on one semiconductor chip. 8 A multiplier that multiplies signals of multiple bits, and a signal provided on the input side of the multiplicand signal and multiplier signal or the output side of the product signal of the multiplier, and multiplies the upper bits by a unit delay amount for each multiple bits. A delay circuit that delays the summand signal by a unit delay amount for each multiple bits, the more the upper bits are delayed, and a delay circuit that delays the summand signal by a unit delay amount for each multiple bits, the more the upper bits. receiving the output signals of a delay circuit, a delay circuit that delays each bit of the summand signal by the same amount of delay, and two delay circuits that delay the summand signal;
A first selector that outputs the output signal specified by the first select signal, and a product signal that is delayed by a unit delay amount for each plurality of bits from the multiplier, and the more significant the higher bit is, the more delayed the product signal is from the first selector. an adder that adds to the output summand signal, a delay circuit that delays the sum signal output from the adder by the same amount of delay for each bit, and a delay circuit that adds the sum signal output from the adder to multiple bits. Receives the output signals of the above two delay circuits, one that delays the lower bit by a unit delay amount for each signal, and the other that delays the sum signal, and outputs the output signal of the one of the delay circuits specified by the second select signal. A digital signal processing circuit comprising: a second selector for output; and a second selector for outputting the signal.