JPH0443430A - Read control system for scratch pad memory - Google Patents

Abstract

PURPOSE:To suppress the deterioration of performance owing to the reduction of the bit width of SPM scratch pad memory by providing an SPM read selector setting a specified value to the specified bit position of an SPM read register as against the number of lack bits in SPM data and an SPM read control means controlling the SPM read selector with a microprogram. CONSTITUTION:The bit width of SPM 3 is 54 bits, for example, and the SPM write register 11 has the size of 54 bits. Data which is read from SPM 3 is controlled by the SPM read control means 14 using specified two bits of the microprogram stored in a control storage register (CSR) 2 at the time of passing the SPM read selector 13. Thus, the deterioration of performance owing to the reduction of the bit width of SPM can be suppressed since the content of the SPM read register 10 can be used as the input of a computing element 4 in a device where the bit width of the SPM read register 10 is larger than the bit of SPM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read control method for a scratch pad memory (SPM). The SPM is a high-speed memory that stores data to assist the arithmetic unit in the arithmetic processing unit of an information processing device.

[Conventional technology]

Conventionally, for SPM read control, an SPM read register with the same bit width as the SPM has been used, so there is no need for particularly complicated control, and data can be read from the SPM and stored as is in the SPM read register. good.

On the other hand, the RkM itself constituting the SPM could be configured to have the same bit width as the SPM read register.

[Problem to be solved by the invention]

In the conventional SPMfi output control method described above, data read from the SPM is stored as is in the read register of the SPM.

However, in recent years, it has become impossible to construct an SPM having the required bit width as in the past due to problems such as the degree of integration of RAM chips, their welfare, and reliability.

Therefore, if the bit width of the SPM read register is correspondingly reduced, the number of bits that can be processed at a time will be reduced, resulting in a decrease in the performance of each processing instruction.

In addition, if you try to change the bit width of the conventional calculation data to the bit width of the conventional calculation data immediately before performing calculation processing while leaving the bit width of the SPM read register as it is, the expansion processing of the SPM read data Or SPM [it requires processing to join the output data with other data, and in the end,
There is a problem in that the performance of arithmetic processing instructions is degraded.

[Means to solve the problem]

The SPM read control method of the present invention includes: a scratch pad memory whose operation is controlled by a microprogram and is composed of a rewritable memory; an SPM read register having a bit width exceeding the bit width of the scratch pad memory; The above S from scratchpad memory
When reading data to the PM read register, a scratch bar is added to a specific bit position of the SPM read register for the number of missing bits of data read from the memory.
It is characterized by comprising: an SPM read selector for setting a predetermined value; and SPM read control means for controlling the SPM read selector by the microprogram.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention, which constitutes an arithmetic processing section of an information processing device.

This arithmetic processing section is controlled by a microprogram stored in the control store (C8) 2 and read out to the control store register (C8B) 2. however,
Microprogram control units other than those around SPM3 are omitted to avoid complicating the drawing.

Now, in this arithmetic processing section, data having a size of 72 bits is processed by the arithmetic unit 4. Of course, the input register 5 of the arithmetic unit 4. Output register 6゜Input selector 7 and 8
．． Output selector 9 and SPM read register 10 are also 7
It has a size of 2 bits. On the other hand, the bit width of SPM3 is 54 bits, and the SPM write register 11 also has a size of 54 bits.

The address to access SPM3Th is SPM write/
It is designated according to the contents of the read (W/R) address register 12. The SPMW/R address register 12 is controlled by the microprogram stored in C8 2.
A strobe and data to be loaded are provided. According to the content of the SPMW/R address register 12 thus determined, 54-bit data is read from the SPM3.

When data read from SPM3 passes through SPM read selector 13, SPM! uses two specific bits of the microprogram stored in C8B,2. The control means 14 executes control as shown in FIG. As a result, the output of sPMWl from the output register 10 can be used as input to the arithmetic unit 4 as is. This situation is shown in Figures 3-A to 3-D. Here, FIG. 3-A will be described in detail as a representative example.

In FIG. 3-A, it is assumed that the input data 31 is expected to be output data 32 composed of a storage portion 35 and an all-0 portion 36 as a calculation result.

In contrast, it is assumed that SPM data 33 is prepared.

In this case, in the SPM data 33, the portion corresponding to the storage portion 35 of the output data 32 is all 1, and the portion corresponding to the all zero portion is all 0. However, since the SPM data 33 in this embodiment has only 54 bits, there is a shortage of 18 bits to correspond to the all-zero portion 36 in the 72-bit output data 32.

Therefore, as shown in FIG.
By setting n+1) to (0,0), SPM
When the data 33 passes through the SPM read selector 13, the missing 18 bits and zeros are added to obtain supplemented SPM data 34.

If there is no function to add the missing 18 bits of zero when passing through the SPM read selector 13, the arithmetic unit 4
data equivalent to the supplemented SPM read data 34 must be created using the .

However, in that case, it is clear that it will take more time than in this embodiment in which the SPM@output selector 13 is used to create the supplemented SPM read data 34f.

Figure 3-B shows the saved part 38 and all 1 as the calculation result.
FIG. 4 is a diagram for a case where the purpose is to obtain output data 37 consisting of a portion 39; In this case, as shown in FIG. 2, CAR pi, )(n, n+1) must be set to (0, 1).

Figure 3-0 shows the saved part 41 and all 0 as the calculation result.
FIG. 4 is a diagram for a case where the purpose is to obtain output data 40 consisting of a portion 42; In this case, the C8 bit (n, n-1-1) must be set to (1, 0) as shown in FIG.

Moreover, FIG. 3-D is a diagram for a case where the purpose is to obtain output data 43 consisting of a storage part 44 and an all-1 part 45 as a calculation result. At this time, as shown in FIG. 2, C8Rby ) (n.

n+1) must be set to (1, l).

FIG. 4 is a diagram representing a second embodiment of the present invention.

In this embodiment, in order to control the output of the SPM read selector 13 (FIG. 2), specific two of the address bits stored in the SPMW/R address register 12 are used.
This embodiment differs from the first embodiment in that bits and bits are used.

Further, FIG. 5 is a diagram showing a third embodiment of the present invention.

This embodiment is different from the first embodiment and the second embodiment in that two specific bits of the data read from the SPM 3 are used to control the output of the SPM read selector 13 (FIG. 2). This is different from the second embodiment.

As described above, in the present invention, the SPM read selector 13
There are four 18-bit bit patterns added in SPM read selector 1 as shown in Figure 2.
It is also possible to add more bit patterns to the SPM data 33 by increasing the number of stages of 3. It is also possible to insert it inside the 82M data 13.

Therefore, according to the present invention, the SPM throat width is
Even in devices where the bit width of the PM read register 10 is larger, the contents of the SPM read register IO can be used as input to the arithmetic unit 4 as is, so performance degradation due to the SPM bit width being smaller than before can be kept to a minimum. It has the effect of being able to

〔Effect of the invention〕

As explained above, the present invention provides an SPM read that, when reading data from the SPM to the SPM read register, specifies the SPM read register and sets a specific value in the upper position for the missing number of bits in the SPM data. selector and SP
SP that controls the M read selector with a microprogram
By having the M read control means, even in a device where the bit width of the SPM read register and the bit width of the input data of the arithmetic unit are larger than the bit width of the SPM,
Since the contents of the SPM read register can be used as is as input to the arithmetic unit, there is an effect that performance deterioration due to the SPM bit width becoming smaller than before can be suppressed to a small level.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the first embodiment of the present invention, and FIG. 2 is a diagram showing the SPM.
A diagram showing the control results of the SPM control means 14 that controls the read selector 13, FIGS. 3-A to 3-D are diagrams showing specific examples realized by the present invention, and FIG. FIG. 5 is a diagram showing a third embodiment of the present invention. l...Control store (C8), 2...
...Control store register (aS 几), 3゛°
°°°° Scratch pad memory (SPM), 4...
...Arithmetic unit, 5...--Input register, 6...
...Output register, 7゜8...Input selector, 9...Output selector, 10...SP
M read register, 11... SPM write register, 12... SPMW/R address register, 13... SPM read selector, 14, 15
゜16...SPM read control means. Agent Patent Attorney Susumu Uchihara Diagram 2 E■==Co1 □ Ro■=Yo=■Co0Go====Kozo=■Co↓ E Engineering=Co■Co↓ Mouth====7Z ↓

Claims (1)

[Scope of Claims] A scratchpad memory configured of a rewritable memory whose operation is controlled by a microprogram, an SPM read register having a bit width exceeding the bit width of the scratchpad memory, and the scratchpad memory. an SPM read selector that sets a predetermined value to a specific bit position of the SPM read register in response to the number of missing bits of data read from the scratch pad memory when reading data from the scratchpad memory to the SPM read register; A scratch pad memory read control system comprising: SPM read control means for controlling the SPM read selector using the microprogram.