JPH0443715A - Counter with holding function - Google Patents

Abstract

PURPOSE:To set an initial value even when an initial set signal is activated simultaneously with a holding signal by controlling the advance and hold of the counted value depending on the holding signal. CONSTITUTION:The holding signal 106 is inputted to an adder 102 as one-bit input via a flip-flop 108 to realize a holding function. The adder 102 makes addition as (output of register 103)+(output of D flip-flop 108) and when the holding signal 106 is inactive (level '1'), the ordinary counted value is incremented by 1, and when the holding signal is active (level 0), the inputted counted value is outputted as it is. Thus, it is not required to interrupt the output of the adder from the input to the register and the set initial value is stored to the register without fail, then even when the initial value setting signal and the holding signal are simultaneously activated, the initial value is set.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter with a hold function.

[Conventional technology]

As a counter that increases the output value by "1" in synchronization with a clock signal, there is a counter that uses an adder. FIG. 4 shows a conventional example of such a counter using an adder.

The basic operation of the conventional counter will be explained below using the same figure. First, by activating the initial value set signal 405, the first selector 407 selectively outputs the n-bit initial value 404 and sets it as a count value 409. When the hold signal 406 is inactive (value "1"), the initial value 404 is
The signal passes directly through the second selector 408 and becomes an input to the register 403 that stores the count result. The output value of this register 403, that is, the n-bit count value 409
becomes the input of adder 402. Adder 402 outputs a value obtained by adding "1" to the count value. Thereafter, the initial value set signal 405 is inactivated and the output of the adder 402 is sent to the first selector 407. It passes through the second selector 408, outputs it as a new count value 409, and inputs it to the register 403 again. As a result, count value 4
゜9 changes from the initial value 404 to “ while synchronizing with the clock.
The value increases by 1".

The hold signal 406 is for controlling the count value 409 so that it does not increase. With this signal,
Changes in the output value (count value) can be suppressed for an arbitrary period of time. When the hold signal 406 is activated (value "O"), the second selector 408 selectively passes the output of the register 403. Therefore, register 403 is
A feedback loop is created in which the output and input are directly connected, and the count value 409 does not change and remains constant.

A timing chart of the above operation is shown in FIG.

[Problem to be solved by the invention]

The operation of the counter having the configuration shown in FIG. 4 when the initial value set signal and the hold signal are simultaneously activated is as follows. Although the initial value of the count passes through the first selector and is output as a count value, it is cut off from the register input by the second selector, so the hold signal is inactive (value "1"). ”), the count value is the value immediately before setting the initial value (this is
) and the count-up continues.

That is, as shown in the timing chart of FIG. 5, the result is the same as when no initial value is set.

However, since the hold signal is a control signal whose purpose is to suppress the increase in the count value, if the hold signal is activated at the time the initial value is set, the set initial value will be held (i.e., the initial value It can be said that it is more desirable to suppress the increase in the value of 0) and to start counting up from the set initial value when the hold signal becomes inactive. A timing chart of such an operation is shown in FIG.

SUMMARY OF THE INVENTION An object of the present invention is to provide a counter with a hold function that allows initial values to be set even if an initial value set signal and a bold signal are simultaneously activated.

[Means to solve the problem]

The counter with a hold function of the present invention includes: a register that stores a count value in synchronization with a clock signal; a D flip-flop that inputs a hold signal and outputs a corresponding 1-bit value in synchronization with the clock signal; An adder inputs the output of the register and the output of the D flip-flop and outputs the sum thereof, and inputs the output of the adder and the initial value of the count, and selects one of them by an initial value set signal. and a selector that selectively outputs the output and inputs the register.

[Effect]

The counter with a hold function of the present invention uses a hold signal to
A hold function is realized by passing it through a D flip-flop and using it as a 1-bit input to an adder. The adder is
(output value of the register) is added (output value of the D flip-flop), and the hold signal is inactive (
When the value is "1"), the normal count value is increased by "1", and the hold signal is activated (value "0").
In this case, the input count value is output as is.

By realizing the hold function with such a configuration,
Unlike the conventional example, there is no need to disconnect the output of the adder from the input of the register, and the set initial value can always be stored in the register. Therefore, even when the initial value set signal and the hold signal are activated at the same time, it is possible to set the initial value and start counting up from the set initial value when the hold signal becomes inactive. becomes.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The counter of the first embodiment includes a register 103 that stores an n-bit count value, and a register 103 that stores an n-bit count value, and a
A D flip-flop 108 that outputs a binary number of bits, an adder 102 that adds the output values of the register 103 and the D flip-flop 108, and an initial value set signal 10.
5 selects either the output of the adder 102 or the initial value of the count and outputs it to the outside as a count value and inputs it to the register 103.

Next, the operation will be explained.

When the initial value set signal 105 is activated, the selector 10
7 selectively outputs an n-bit initial value 104 and sets it as a count value 109. This count value 109 is the register 10
3 input. Furthermore, this count value 109 is output by the register 103 to the adder 102 in synchronization with the clock signal 101. Hold signal 106 is the input of D flip-flop 108, and the output of D flip-flop 108 is the 1-bit long input of adder 102. The adder 102 is an arithmetic unit that outputs the sum of an n-bit binary number and a 1-bit binary number.
bit output value) + (1-bit output value (=1) of D-Fliruff"70 knob 108).

Therefore, the hold signal 106 is inactive, that is, the value is "1".
In this case, the value obtained by adding "bi" to the current count value will be output. If the initial value set signal 105 is inactive at that time, the output of the adder 102 will be the count value 109.
Then, the count-up operation continues in the same manner.

When the hold signal 106 is activated during count-up, that is, when the value becomes "0", the adder 102 outputs (output value of register 103) + (D flip-flop 1).
Since the output value (=O) of 08 is calculated, the current count value continues to be output as is. Therefore, the operation shown in the time chart of FIG. 2 can be realized.

Next, consider a case where the initial value set signal 105 and the hold signal 106 are activated simultaneously.

The initial value 104 passes through the selector 107 and becomes the count value 1.
09 and becomes an input to the register 103. Since the hold signal 106 is active, that is, the value is "0", the D flip-flop 108 is synchronized with the clock and has the value "0".
0", and the adder 102 outputs the output value of the register 103 as is. In other words, the adder 102
The output value of 2 is equal to the initial value 104. Therefore, even if the initial value set signal 105 is inactivated and the selector 107 selectively passes the output of the adder 102, the count value 109 remains the initial value. It remains 104.

When the hold signal 106 becomes inactive (value "1"), the adder 102 starts adding "1", so the value obtained by counting up the initial value 104 becomes the clock signal 101.
It will be output in sync with. Therefore, the operation shown in the timing chart of FIG. 3 can be realized.

In the present invention, the hold signal 106 is activated when the value is "0", but by connecting an inverter to the output section (or input section) of the D flip-flop 108, the hold signal 106 is activated when the value is "1". It is also possible to make it active.

〔Effect of the invention〕

In a conventional counter with a hold function, if the initial value set signal and the hold signal were activated at the same time, the initial value could not be set. This is because the configuration is such that the output of the adder cannot be set to the register that stores the count value once the hold signal is activated.

The counter with a hold function of the present invention inputs a hold signal to an adder to control whether "1" is added to the count value or not, and the output of the adder is always set to a register. It has become. Therefore, even if the initial value set signal and hold signal are activated at the same time,
It becomes possible to set an initial value and suppress an increase in the initial value.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a basic timing chart of a counter with a hold function,
FIG. 3 is a timing chart when the signal for setting the initial value and the hold signal are activated simultaneously in the counter with a hold function of the present invention, FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a diagram showing the conventional example. FIG. 7 is a timing chart when a signal for setting an initial value and a hold signal are activated at the same time. 101.401...Clock signal, 102,402...
...Adder, 103.403...Register, 104°404...Initial value, 105,405...Initial value set signal, 106.406...Hold signal, 107.
...Selector, 407...First selector, 408.
...Second selector, 108...D flip-flop, 109.409...Count value.

Claims (1)

[Claims] A register that stores a count value in synchronization with a clock signal, a D flip-flop that inputs a hold signal and outputs a corresponding 1-bit value in synchronization with the clock signal, and a combination of the output of the register and the D flip-flop. an adder that inputs the output and outputs the sum thereof; and an adder that inputs the output of the adder and the initial value of the count, selectively outputs one of the two by an initial value set signal, and outputs the input of the register. 1. A counter with a hold function, comprising a selector for controlling the increment and hold of the count value according to the value of the hold signal.