JPH0444046U - - Google Patents
Info
- Publication number
- JPH0444046U JPH0444046U JP1990086002U JP8600290U JPH0444046U JP H0444046 U JPH0444046 U JP H0444046U JP 1990086002 U JP1990086002 U JP 1990086002U JP 8600290 U JP8600290 U JP 8600290U JP H0444046 U JPH0444046 U JP H0444046U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reset signal
- reset
- signal
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Maintenance And Management Of Digital Transmission (AREA)
Description
第１図は本考案に係る異常検出回路の一実施例
を示す回路構成図、第２図は第１図の回路の動作
を示すタイムチヤートである。
１……下位機器、１１……ＣＰＵ、１２……Ｗ
ＤＴ回路、１３……シリアル通信用ＩＣ、１４…
…インバータ、１５……ワンシヨツト回路、１６
……パワーオンリセツト回路、１７……ＮＯＲゲ
ート、１８……ＲＯＭ、１９……ＲＡＭ、２……
上位機器。
FIG. 1 is a circuit configuration diagram showing an embodiment of an abnormality detection circuit according to the present invention, and FIG. 2 is a time chart showing the operation of the circuit of FIG. 1. 1...lower device, 11...CPU, 12...W
DT circuit, 13... Serial communication IC, 14...
...Inverter, 15...One shot circuit, 16
...Power-on reset circuit, 17...NOR gate, 18...ROM, 19...RAM, 2...
Upper level equipment.
Claims (1)
回路において、 下位機器を制御するＣＰＵと、 このＣＰＵからのリセツト信号でクリアされ、
入力クロツクによりタイムアツプしたときに上位
機器にステータス信号を通知するＷ
ＤＴ回路と、 シリアルデータをパラレル信号に変換するシリ
アル通信用ＩＣと、 前記ＷＤＴ回路から出力される信
号がアクテイブのときのみ動作し、上位機器から
データが送られたときをトリガとし、外部リセツ
ト信号を出力するワンシヨツト回路と、 電源がオンになつたときにリセツト信号を出力
するパワーオンリセツト回路と、 前記ワンシヨツト回路からの外部リセツト信号
と前記パワーオンリセツト回路からのパワーオン
リセツト信号を入力として、前記ＣＰＵにリセツ
ト信号を出力する回路とを具備し、 上位機器は前記ＷＤＴ回路からの
信号がアクテイブになつたときに異常を検出した
のちダミーコードを送出し、下位機器はこのダミ
ーコードの入力をトリガとして前記ＣＰＵをリセ
ツトすることを特徴とする異常検出回路。[Claim for Utility Model Registration] In an abnormality detection circuit that detects and recovers from abnormalities in lower-order equipment, a CPU that controls the lower-order equipment and a reset signal from this CPU clear the circuit,
W that notifies the host device of a status signal when time-up occurs due to the input clock.
The DT circuit, a serial communication IC that converts serial data into a parallel signal, and the WDT circuit operate only when the signals output from the circuit are active, and are triggered when data is sent from the host device, and an external reset signal is activated. a power-on reset circuit that outputs a reset signal when the power is turned on; an external reset signal from the one-shot circuit and a power-on reset signal from the power-on reset circuit are input; and a circuit that outputs a reset signal to the CPU, the upper device detects an abnormality when the signal from the WDT circuit becomes active, and then sends out a dummy code, and the lower device receives the input of this dummy code. An abnormality detection circuit characterized in that the CPU is reset as a trigger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990086002U JPH0444046U (en) | 1990-08-15 | 1990-08-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990086002U JPH0444046U (en) | 1990-08-15 | 1990-08-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444046U true JPH0444046U (en) | 1992-04-14 |
Family
ID=31817424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990086002U Pending JPH0444046U (en) | 1990-08-15 | 1990-08-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444046U (en) |
-
1990
- 1990-08-15 JP JP1990086002U patent/JPH0444046U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS57155601A (en) | Car safety device | |
| EP0351984A3 (en) | Programmable interface for computer system peripheral circuit card | |
| DE69530141D1 (en) | Integrated processor that provides indexes of internal activities to an external power control bus | |
| ES464099A1 (en) | Input/output interface connector circuit for repowering and isolation | |
| JPH0444046U (en) | ||
| JPS58108724U (en) | Digital protective relay device | |
| JPS5523561A (en) | Micro computer system | |
| JPS54945A (en) | Integrated circuit providing output control function | |
| JPS5727322A (en) | Input and output controlling system of computer | |
| KR970008509B1 (en) | Resetting apparatus for micom | |
| JPS53149739A (en) | Computer system | |
| JPS63191245A (en) | Resetting control system for device being in runaway state | |
| JPS55103618A (en) | Multi-processor system | |
| JPS5682955A (en) | Multiple computer system | |
| CN116243635A (en) | An industrial camera starting system | |
| JPS57137916A (en) | Computer for car | |
| JPS5359400A (en) | Annunciator | |
| JPS62162728U (en) | ||
| JP2501666Y2 (en) | Unit duplication device | |
| EP0997818A4 (en) | Computer monitor device | |
| JPS5464440A (en) | Interrupt control system of electronic control unit | |
| JPS53109448A (en) | Information processor | |
| JPH03127938U (en) | ||
| JPS5652443A (en) | Parity addition system | |
| JPS57117025A (en) | Information processing device |