JPH044405U - - Google Patents

Info

Publication number
JPH044405U
JPH044405U JP4436390U JP4436390U JPH044405U JP H044405 U JPH044405 U JP H044405U JP 4436390 U JP4436390 U JP 4436390U JP 4436390 U JP4436390 U JP 4436390U JP H044405 U JPH044405 U JP H044405U
Authority
JP
Japan
Prior art keywords
signal lines
transmission line
dielectric layer
ground layer
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4436390U
Other languages
Japanese (ja)
Other versions
JP2603022Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990044363U priority Critical patent/JP2603022Y2/en
Publication of JPH044405U publication Critical patent/JPH044405U/ja
Application granted granted Critical
Publication of JP2603022Y2 publication Critical patent/JP2603022Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の実施例の一部を示す斜視図
、第2図はこの考案の他の実施例の一部を示す斜
視図、第3図は第2図中の1本の信号線に対する
伝送路と等価な同軸伝送路を示す断面図、第4図
はこの考案の更に他の実施例の一部を示す断面図
、第5図はこの考案をマイクロストリツプライン
形式に適用した例を示す斜視図、第6図は従来の
プリント基板伝送路の一部を示す斜視図、第7図
は提案されているプリント基板伝送路を示す斜視
図である。
Fig. 1 is a perspective view showing a part of an embodiment of this invention, Fig. 2 is a perspective view showing a part of another embodiment of this invention, and Fig. 3 shows one signal line in Fig. 2. Fig. 4 is a sectional view showing a part of a further embodiment of this invention, and Fig. 5 is an example of applying this invention to a microstripline type. 6 is a perspective view showing a part of a conventional printed circuit board transmission path, and FIG. 7 is a perspective view showing a proposed printed circuit board transmission path.

Claims (1)

【実用新案登録請求の範囲】 誘電体層の一面に複数の信号線が形成され、上
記誘電体層の他面に上記各信号線と対向し、これ
よりも幅の広い接地層がそれぞれ互いに分離され
て形成され、 上記各信号線とその対向する上記接地層とでそ
れぞれ独立した伝送路が構成されているプリント
基板伝送路。
[Claims for Utility Model Registration] A plurality of signal lines are formed on one side of the dielectric layer, and a ground layer that is wider than the signal lines and is separated from the other side of the dielectric layer, respectively. A printed circuit board transmission line, wherein each of the signal lines and the ground layer facing each other form an independent transmission line.
JP1990044363U 1990-04-25 1990-04-25 Printed circuit board transmission line Expired - Lifetime JP2603022Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990044363U JP2603022Y2 (en) 1990-04-25 1990-04-25 Printed circuit board transmission line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990044363U JP2603022Y2 (en) 1990-04-25 1990-04-25 Printed circuit board transmission line

Publications (2)

Publication Number Publication Date
JPH044405U true JPH044405U (en) 1992-01-16
JP2603022Y2 JP2603022Y2 (en) 2000-02-14

Family

ID=31557597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990044363U Expired - Lifetime JP2603022Y2 (en) 1990-04-25 1990-04-25 Printed circuit board transmission line

Country Status (1)

Country Link
JP (1) JP2603022Y2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082525A (en) * 2009-10-12 2011-04-21 Internatl Business Mach Corp <Ibm> Ceramic package, method for reducing joint noise in ceramic package and controlling impedance discontinuity, and computer program (noise joint reduction and impedance discontinuity control in high-speed ceramic module)
JP2013510407A (en) * 2009-11-06 2013-03-21 モレックス インコーポレイテド Multilayer circuit member and assembly therefor
JP2013089841A (en) * 2011-10-20 2013-05-13 Kyocer Slc Technologies Corp Wiring board
JPWO2021182158A1 (en) * 2020-03-11 2021-09-16
JPWO2021182157A1 (en) * 2020-03-11 2021-09-16
WO2023037852A1 (en) * 2021-09-07 2023-03-16 株式会社村田製作所 Multilayer substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158502A (en) * 1980-05-12 1981-12-07 Junkosha Co Ltd Strip line
JPS57143901A (en) * 1981-02-27 1982-09-06 Junkosha Co Ltd Strip line

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158502A (en) * 1980-05-12 1981-12-07 Junkosha Co Ltd Strip line
JPS57143901A (en) * 1981-02-27 1982-09-06 Junkosha Co Ltd Strip line

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082525A (en) * 2009-10-12 2011-04-21 Internatl Business Mach Corp <Ibm> Ceramic package, method for reducing joint noise in ceramic package and controlling impedance discontinuity, and computer program (noise joint reduction and impedance discontinuity control in high-speed ceramic module)
JP2013510407A (en) * 2009-11-06 2013-03-21 モレックス インコーポレイテド Multilayer circuit member and assembly therefor
JP2013089841A (en) * 2011-10-20 2013-05-13 Kyocer Slc Technologies Corp Wiring board
JPWO2021182158A1 (en) * 2020-03-11 2021-09-16
JPWO2021182157A1 (en) * 2020-03-11 2021-09-16
US11751321B2 (en) 2020-03-11 2023-09-05 Murata Manufacturing Co., Ltd. Resin multilayer substrate
WO2023037852A1 (en) * 2021-09-07 2023-03-16 株式会社村田製作所 Multilayer substrate
JPWO2023037852A1 (en) * 2021-09-07 2023-03-16
US12439505B2 (en) 2021-09-07 2025-10-07 Murata Manufacturing Co., Ltd. Multilayer substrate

Also Published As

Publication number Publication date
JP2603022Y2 (en) 2000-02-14

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