JPH0444112A - Key input processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a key input processing circuit for reading key input data by a microcomputer.

<Prior art> In a keyboard arranged in a matrix, data corresponding to pressed keys is sent to a microcomputer.
When performing reading processing using , it is necessary to eliminate chattering that accompanies key presses and to correctly obtain data corresponding to the pressed keys.

Traditionally, these requirements have been achieved through a combination of software and hardware, with software being the main focus for low cost measures, and hardware-based measures for increasing speed and reducing the software load. It is being

Under these circumstances, a hardware-based main input processing circuit that eliminates chattering and detects changes in key states while reducing the software load as much as possible is disclosed in, for example, Japanese Patent Laid-Open No. 62-31416. Disclosed.

<Problems to be Solved by the Invention> Since the key input processing circuit disclosed herein has a configuration in which the states of all keys on the keyboard are latched in the latch means, the latch means requires a large capacity and also has a large capacity. In order to obtain data corresponding to a pressed key, the microcomputer must read as many lines as there are rows on the keyboard, and it cannot be said that the software load is sufficiently reduced.

The present invention was created in view of such circumstances, and
It is an object of the present invention to provide a key input processing circuit that can eliminate chattering using a small-capacity latch means, and that can accurately obtain data corresponding to a pressed key with a small number of readings by a microcomputer. do.

<Means for Solving the Problems> The key input processing circuit according to the present invention includes a means for detecting data corresponding to a pressed key from a keyboard arranged in a matrix, and a means for detecting data corresponding to a pressed key from a keyboard arranged in a matrix. means for latching the data in two stages after a time longer than the time has elapsed, means for comparing the data latched in the two stages, and means for latching the data when the compared data match, and transmitting the data to the microcomputer
It is characterized by comprising means for outputting an interrupt signal to the microcomputer so as to be read by the microcomputer.

<Operation> Since the detected data is latched after a time longer than the chattering occurrence time has elapsed, chattering is eliminated. Data is latched in two stages, and when both data match, the data is read by the microcomputer, so it is possible to accurately obtain data corresponding to the pressed key. Since only the data corresponding to the pressed key is latched, the capacity of the latching means can be reduced. Since the latch data is read when the microcomputer is interrupted, the software load is reduced.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a key input processing circuit showing one embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.

This key input processing circuit that processes input signals from a keyboard 1 arranged in a matrix has a clock generator 2 that generates two types of clocks. The first clock generated by the clock generator 2 has a cycle sufficiently longer than the chattering occurrence time, and is sent to the counter 3, and the second clock has a cycle shorter than the chattering occurrence time, and is sent to the counter 3. Sent to register 9.

The counter 3 repeatedly counts up from zero to a predetermined value in response to the first clock input from the clock generator 2. The determined value is a value determined by the number of lines on the keyboard 1, and is 1 for up to 4 lines, 2 for up to 8 lines, and 3 for up to 16 lines. The output of the counter 3 passes through a transparent latch 4 to a decoder 5.
The data is sent to registers 10 and 11.

The transparent latch 4 functions to pass data from the counter 3 when the output of a key input detection circuit 8, which will be described later, is at a low level, and to hold the data from the counter 3 when the output is at a high level. The decoder 5 inputs and decodes the output of the transparent latch 4, and sets each row of the keyboard 1 to a low level in a time-division manner, thereby scanning the 10 rows of the keyboard. Decoder 5
The size of is also determined by the number of lines on the keyboard, for example 8
For rows, 3t08 is required.

Signals from each column of the keyboard 1 pass through an input buffer 6 and are input to an encoder 7 and a key input detection circuit 8. When no key on the keyboard 1 is pressed, all inputs to the key input detection circuit 8 become high level. At this time, the output C of the key input detection circuit 8 becomes low level, clearing the shift register 9, and setting the transparent latch 4 to transparently pass the data of the counter 3. If a key is pressed,
The output C of the key input detection circuit 8 becomes high level, and the clear state of the shift register 9 is released, and the transparent latch 4 is put into a holding operation, and its row line scanning operation is stopped.

The signals from each column of the keyboard 1, which are input to the encoder 7 through the input huffer 6, are sent to a register 10.11.

When the clear state is released, the shift register 9 starts counting the second clock transmitted by the clock generator 2, and when a certain number of clocks are counted, the first output d changes from a low level to a high level. The data in the encoder 7 is latched into the register 10. The count time (Tl in FIG. 2) at this time is set longer than the chattering occurrence time. When the shift register 9 further counts a certain number of clocks (count time is T2 in FIG. 2), the second output e of the shift register 9 changes from low level to high level and outputs the second output e to the encoder 7.
The data in the register 11 is latched.

Data f in register 10 is sent to comparator 12 and third stage register 13, and data g in register 11 is sent only to comparator 12.

The comparator 12 compares the data f and g latched in the registers 10 and 11, and when the data f and g match, the output changes from low level to high level. The output of the comparator I2 that has changed to a high level becomes a latch signal for the third stage register 13, causing the data in the register 10 to be latched into the third stage register 13, and also serves as a clock input to the flip-flop (FF) 14. Therefore, the output j of the flip-flop (FF) 14 is changed from low level to high level.

The output j of the flip-flop (FF) 14 that has changed to high level is an interrupt signal I to the microcomputer.
Become an NT. The microcomputer knows when a key has been input by receiving the interrupt signal INT.
Select signal for register 13! The address assigned to register 13 is read in order to obtain key input data. At this time, the read strobe signal k from the microcomputer becomes low level, and the data j in the register 13 is output to the data bus of the microcomputer, so that the microcomputer obtains data corresponding to the key input. . At the same time, in response to the REIT strobe signal, the flip-flop (FF) 14 is reset to 1.
At the same time as canceling the interrupt signal INT, the contents of the register 11 are cleared and its output g is set to zero.

When no key on the keyboard 1 is pressed, all inputs to the key input detection circuit 8 are at high level, and its output C is at low level. Therefore, the transparent latch 4 is in a state of transparently passing data from the counter 3, and the shift register 9 is in a clear state. By transparently passing the data from the counter 3 through the transparent latch 4, the decoder 5 sets each row of the keyboard 1 to a low level in a time-divisional manner, and scans the rows of the keyboard 1.

Now, when the key on the row line a that has been set to low level by the decoder 5 is pressed, the signal on the column line corresponding to the pressed key passes through the input buffer 6 and is sent to the encoder 7 with chattering. and is input to the key input detection circuit 8. By inputting the signal to the key input detection circuit 8, the output C of the key input detection circuit 8 becomes high level.
At the same time that the clear state of the shift register 9 is released, the transparent latch 4 enters the holding operation, and the row line scan by the decoder 5 is stopped.

When the clear state of the shift register 9 is released, the second clock from the clock generator 2 causes the shift I.
When the register 9 starts operating and a certain number of clocks are input to the shift register 9 (TI in FIG. 2 as time),
The first output d of the shift register 9 changes from low level to high level. By this rising edge of the output d, the output data of the counter 3 held in the transparent transistor 4 and the column line signal encoded by the encoder 7 are latched into the register 10. Since the chattering in the column line signal disappears between the time the column line signal is input to the key input detection circuit 8 and the time it is input to the register 10, the column line signal latched by the register 10 Does not include chattering.

When a fixed number of clocks are further input to the shift register 9 (time T2 in FIG. 2), the second output e of the shift register 9 changes from low level to high level.

By this rising edge of the output e, the output data of the counter 3 held in the transparent latch 4 and the column line signal encoded by the encoder 7 are latched into the register 11. The column line signals latched in the register 11 also do not contain chattering.

When data f latched in register 10 and data g latched in register 11 match, comparator 1
The output of 2 changes from low level to high level. As the output of the comparator 12 changes to high level, the data in the register 10 is latched into the third stage register 13, and the flip-flop (FF) 14
The output j changes from low level to high level.

When the output j of the flip-flop (FF) 14 changes to high level, an interrupt signal INT is input to the microcomputer, which causes the microcomputer to read the address assigned to the register 13 to obtain key input data. I Read.

At this time, lead source 1 from the microcomputer
When the lobe signal k becomes low level and the data i in the register 13 is output to the data bus of the microcomputer, the microcomputer obtains data corresponding to the key input. At the same time, flip-flop (F
F) 14 is reset, the interrupt signal INT is released, and the contents of the register 11 are cleared.

By clearing the contents of the register 11, correct processing is possible even if the next nine key input values are the same as the current value.

If the data f latched in the register 10 and the data g latched in the register 11 do not match, the output of the comparator 12 remains at a low level, and the data in the register 10 is latched into the third stage register 13. Not done. Furthermore, since the output j of the flip-flop (FF) 14 is maintained at a low level, no interrupt signal INT is input to the microcomputer, and no key input is read by the microcomputer.

When the key press is released, the output C of the key input detection circuit 8 returns to a low level, and the shift register 9 becomes a clear state. At the same time, the transparent latch 4 becomes transparent. As a result, the row line scan by the decoder 5 is restarted, and the state becomes ready for key input.

The data i in the register 13 that is output to the data bus of the microcomputer does not contain any chattering, and the key input signal is latched in two stages in the registers 10 and 11, and when the two data match, Since the data is latched in the register 13, the data corresponding to the pressed key can be accurately read by the microcomputer. Furthermore, although the configuration allows for accurate reading, only the data corresponding to the pressed key is latched, so the capacity of the register is reduced, and furthermore, it is possible to read the register when the microcomputer receives an interrupt. Because data can be obtained only by
The software load is also reduced.

FIG. 3 is a block diagram of a key input processing circuit showing another embodiment of the present invention, and FIG. 4 is a timing chart for explaining its operation.

This key input processing circuit has a configuration in which the register 13 and flip-flop (FF) 14 of the key input processing circuit shown in FIGS. 1 and 2 are replaced with a first-in-first-out register (FIFO register) 15. There is.

The FIFO register 15 has a configuration in which the output of the comparator 12 is input as a latch signal, and
When data f and g latched in match, comparator 1
When the output of the register 2 changes from low level to high level, the data in the register 10 is latched. register 1
When the data in 0 is latched into the FIFO register 15, the output m of the FIFO register 15 (signal indicating that data is latched) changes from low level to high level, which causes an interrupt signal to the microcomputer. It becomes INT.

The microcomputer recognizes that there has been a key input.
It is known by receiving the interrupt signal INT, and the address assigned to the FIFO register 15 is read in order to obtain key input data by the signal 1 to select 1. At this time, the strobe signal k from the microcomputer becomes low level, and the data i in the FIFO register 15 is output to the data bus of the microcomputer. get.

The interrupt signal INT sent from the FIFO register 15 to the microcomputer is
is released when reading the data in the FIFO register 15 and when there is no more data latched in the FIFO register 15 (the output m of the FIFO register 15 becomes low level). However, if the data is latched in the FTP0 register 15 after the microcomputer reads the data in the FIFO register 15, this signal becomes high level again.

When a key on the keyboard 1 is pressed once, the register 1
The data in 0 is latched into the FIFO register 15, and the key input is read by the microcomputer. At this time, the data in the register 10 latched in the FIFO register 15 does not contain chattering, and the key input signal is latched in two stages in the registers 10 and 11, and only when the two data match. Since the data is latched in the FIFO register 15, the data corresponding to the pressed key can be accurately read by the microcomputer. Further, the capacity of the register is small and the burden on the software is reduced, which is similar to the key input processing circuit of FIGS. 1 and 2.

When the first key press causes an interrupt to the microcomputer, the microcomputer is executing a program with a higher priority than this interrupt and cannot read the key input data immediately. If the key is pressed for the second or third time, Figures 1 and 2 will be displayed.
In the key input processing circuit shown in the figure, the second and third key input data are lost, but in the key input processing circuits shown in FIGS. 3 and 4, such a problem does not occur.

That is, the first key input data is stored in the FIFO register 15.
The second and third ;)-one card data are latched in the first stage of the FIF○ register 15, respectively. The microcomputer is now ready to process key input data, and the FTFO register 1
When the address assigned to 5 is read, the key input data for the first row is obtained. Along with this, the data in the second stage of the FIFO register 15 becomes the first stage, and the data in the third stage becomes the second stage.
The output m of the FIFO register 15, which has become low level during reading, becomes high level again.

As a result, the microcomputer is interrupted again, and the second key input data is read from the FIFO register 15 by the microcomputer. The FIFO register 15 sequentially sends the data in the second stage to the first stage, and sends the interrupt signal INT to the microcomputer again.

The microcomputer reads the data in the FIFO register 15 again to obtain the third key input data.

When the third key input data is obtained, there is no latch data in the FIF○ register 15, so the FIF
The output m of the O register 15 is maintained at a low level, and no interrupt signal INT is sent to the microcomputer until the next key is pressed.

In this way, the key input processing circuits in FIGS. 3 and 4 are
Chattering can be eliminated by a small capacity latch means, and
In addition to being able to accurately obtain the data corresponding to the pressed key with only a few readings by the microcomputer, it is also useful when a program with a high priority and a long processing time is being executed on the microcomputer. Even if there are multiple keystrokes, each data is retained in sequence,
Since the correct data is read by the microcomputer in the order in which the keys were pressed, the software load on the key input processing circuit is reduced.

<Effects of the Invention> As described above, in the case of the key input processing circuit according to the present invention, only the data corresponding to the pressed key is latched, so the capacity of the latching means is reduced, simplifying the circuit and reducing costs. reduction is possible. Since the latch data is read when the microcomputer is interrupted, the software load is reduced and real-time performance is improved. Furthermore, since latching is performed after a time longer than the chattering occurrence time has elapsed in response to a key input, chattering is eliminated.

Data is latched in two stages, and when both data match, the data is read by the microcomputer, so it is possible to accurately obtain data corresponding to the pressed key.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a key input processing circuit showing one embodiment of the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a key input processing circuit showing another embodiment of the present invention. The block diagram of the circuit and FIG. 4 are timing charts for explaining its operation. 1 ・ ・ ・ 8 ・ ・ 10.11. 12. . . . 15. . . Keyboard key input detection circuit 13...Register comparator FIFO register

Claims (1)

[Claims] (1) A means for detecting data corresponding to a pressed key from a keyboard arranged in a matrix, and a means for latching the detected data in two stages after a time longer than the chattering occurrence time; and means for latching the data when the compared data match and outputting an interrupt signal to the microcomputer so that the data can be read by the microcomputer. A key input processing circuit characterized by: