JPH0444260A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0444260A
JPH0444260A JP14851090A JP14851090A JPH0444260A JP H0444260 A JPH0444260 A JP H0444260A JP 14851090 A JP14851090 A JP 14851090A JP 14851090 A JP14851090 A JP 14851090A JP H0444260 A JPH0444260 A JP H0444260A
Authority
JP
Japan
Prior art keywords
electrode
layer
thin film
resistor
film resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14851090A
Other languages
Japanese (ja)
Inventor
Norio Yamamoto
憲郎 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14851090A priority Critical patent/JPH0444260A/en
Publication of JPH0444260A publication Critical patent/JPH0444260A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the contact resistance of an Al electrode, further an Al electrode of a first layer and an Al wiring electrode of a second layer with a CrSiX thin film resistor by first the resistor on an insulating film, and then forming the Al wiring electrode of the second layer thereon. CONSTITUTION:An Si substrate 1 has an oxide insulating film 2, an electrode forming opening window 2 is opened at the film 2, sputtered to cover it with a thin film, selectively reactive ion etched to expose an opening window 3, and a thin film resistor 4 is formed (a). Then, after an SiO2 thin film generated by spontaneous oxidation in the bottom of the window 3 is removed, it is covered with an Al film by sputtering, selectively wet etched to form an Al electrode 5 of a first layer (b). It is coated with photosensitive polyimide 6, exposed, developed, thermally cured, then selectively etched to expose an Al electrode 5 and two electrode regions 7 to be formed on the resistor (c). Then, after thin layers of spontaneously oxidized Cr2O3 on the surfaces of the electrode 5 and the resistor 4 are removed by RF etching, it is covered with an Al film under the same conditions as those in the paragraph (b), patterned, and wiring electrodes 8, 8' a second layer are formed.

Description

【発明の詳細な説明】 〔概 要〕 CrS+、D(Xは1〜2の範囲の数を表す)薄膜抵抗
体を有する半導体装置の製造方法に関し、CrSi、0
薄膜抵抗体とl’i極との接触抵抗を改良することを目
的とし、 第1の発明の方法は、絶縁膜の開口窓に第1層のAA主
電極形成し、感光性ポリイシドを使用して平坦化層間絶
縁膜を形成し、選択的エツチングにより、CrSi、0
薄膜抵抗体の電極を形成すべき領域および第1層のAβ
電極を露出させ、5in2換算60〜120人の深さま
でRFエツチングを行って、自然酸化されて生成した抵
抗体表面のCr2O3と第1層のAj’電極表面のAl
2O,との薄層を除去した後に、第2層の配線電極を形
成するように構成し、 第2の発明の方法は、絶縁膜の開口窓、およびCrS+
、D薄膜抵抗体の電極を形成すべき領域に、厚さ100
〜5000人の第1層のAI主電極形成し、RFエツチ
ングを行ってこれらの電極表面に自然酸化されて生成し
たA I 、03薄層を除去した後に、CrS+、0薄
膜をスパッタリングし、パターニングして薄膜抵抗体を
形成し、さらに5iO7換算60〜120人の深さまで
RFエツチングを行って、第1層のAβ電極およびCr
Si、O薄膜抵抗体の表面に自然酸化されて生成したA
l2O2とCr2O3との薄層を除去した後に、第2層
の配線電極を形成するように構成する。
Detailed Description of the Invention [Summary] A method for manufacturing a semiconductor device having a thin film resistor of CrS+,D (X represents a number in the range of 1 to 2).
Aiming at improving the contact resistance between the thin film resistor and the l'i electrode, the method of the first invention forms the first layer of AA main electrode in the opening window of the insulating film and uses photosensitive polyide. CrSi, 0
Region where the electrode of the thin film resistor is to be formed and Aβ of the first layer
The electrode is exposed and RF etching is performed to a depth of 60 to 120 people in terms of 5in2 to remove Cr2O3 on the surface of the resistor produced by natural oxidation and Al on the surface of the first layer Aj' electrode.
The method of the second invention is configured to form a second layer wiring electrode after removing a thin layer of CrS+ and CrS+.
, D with a thickness of 100 mm in the area where the electrodes of the thin film resistor are to be formed.
~5000 people formed the first layer of AI main electrodes, performed RF etching to remove the naturally oxidized AI,03 thin layer on the electrode surfaces, and then sputtered and patterned a CrS+,0 thin film. to form a thin film resistor, and further perform RF etching to a depth of 60 to 120 mm in terms of 5iO7 to remove the first layer of Aβ electrodes and Cr.
A produced by natural oxidation on the surface of Si, O thin film resistor
After removing the thin layer of 12O2 and Cr2O3, a second layer of wiring electrodes is formed.

〔産業上の利用分野〕[Industrial application field]

本発明はCrSi、O薄膜抵抗体を有する半導体装置の
製造方法に関する。近年、薄膜抵抗体は、シート抵抗が
、1にΩ/四以上で、かつ抵抗の温度係数が±1oop
pm/を程度に小さいことが要求されている。これには
(:r3iXまたはCrS、0 (Xは1〜2の範囲の
数を表す)が使用される。
The present invention relates to a method for manufacturing a semiconductor device having a CrSi,O thin film resistor. In recent years, thin film resistors have a sheet resistance of 1Ω/4 or more and a temperature coefficient of resistance of ±1oop.
pm/ is required to be as small as possible. For this, (:r3iX or CrS,0 (X represents a number in the range 1 to 2) is used.

〔従来の技術〕[Conventional technology]

CrSi註薄膜抵抗体を有する半導体装置の製造方法に
おいては、CrSi、O薄膜と^β電極との接触抵抗が
大きいことが問題になっていた。これはCrSi、0ま
たはiの表面に自然酸化によって針、03またはA I
t z03の薄層を生成し、これらが絶縁性を有するた
tである。また、第1層の^l電極および(:rS+、
0薄膜抵抗体を形成した後に、平坦化層間絶縁膜を形成
し、これに第2層の電極形成用開口窓をあけて配線電極
を形成するが、自然酸化によって、第1層のAβ電極と
CrS+、0薄膜抵抗体との表面にAl2O2とCr2
O3との薄層が生成する。
Note: In the method of manufacturing a semiconductor device having a CrSi thin film resistor, a problem has been that the contact resistance between the CrSi, O thin film and the ^β electrode is large. This is a needle, 03 or A I by natural oxidation on the surface of CrSi, 0 or i.
This produces thin layers of t z03 and these have insulating properties. In addition, the ^l electrode of the first layer and (:rS+,
0 After forming the thin film resistor, a flattened interlayer insulating film is formed, and a wiring electrode is formed by opening an opening window for forming the second layer electrode. Al2O2 and Cr2 on the surface of CrS+,0 thin film resistor
A thin layer of O3 is formed.

これを除去するにはRFエツチングを行えばよいが、も
し第1のAI電極形成用開口窓があいたままでRFエツ
チングを行えば、バルクSi にダメージを与える欠点
もあった。なお、PSG層間絶縁膜の化学気相成長(C
VD)による生成工程は、1−PSGの塗布、B−PS
Gの塗布、液体OCDによる平坦化、および制御された
反応性イオンエツチングを行うことが必要であり、繁雑
な工程であった。
This can be removed by RF etching, but if RF etching is performed with the opening window for forming the first AI electrode open, it also has the disadvantage of damaging the bulk Si. In addition, chemical vapor deposition (C
The production process by VD) includes coating of 1-PSG, B-PS
It was a complicated process, requiring G coating, liquid OCD planarization, and controlled reactive ion etching.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は、CrS+、Q薄膜抵抗体を有する半導体装置
の製造においで、CrSi、0薄膜抵抗体とAI!It
、さらに第1層のAβ電極と第2層のAl配線電極との
接触抵抗を改良することを主要な目的とする。
The present invention is applicable to manufacturing a semiconductor device having a CrS+,Q thin film resistor and an AI! It
Furthermore, the main objective is to improve the contact resistance between the first layer Aβ electrode and the second layer Al wiring electrode.

C課題を解決するたとの手段〕 上記課題は、CrSi、0薄膜抵抗体を有する半導体装
置の製造方法であって、(イ)絶縁膜に電極形成用開口
窓をあけた81基板tに、CrSi、O(Xは1〜2の
範囲の数を表す)薄膜をスパッタリングし、パターニン
グして、Cr51.D薄膜抵抗体を形成し、(ロ)0.
5〜5.0%HFで前処理した後に、第1層のlをスパ
ッタリングし、パターニングして開口窓に第1層の^1
電極を形成し、(ハ)感光性ポリイミドを塗布し、露光
・現像し、熱硬化させて、平坦化層間絶縁膜を形成し、
次に選択的エツチングにより、CrSi、0薄膜抵抗体
の電極形成領域と第1層の^β電極とを露出させ、(ニ
)自然酸化されて生成した、CrSi、0薄膜抵抗体表
面のCr2O,と、第1層の^l電極表面のA I 2
03 との薄層を8102換算60〜120人の深さま
でRFエツチングにより除去した後に、(ホ)第2層の
^!をスパッタリングし、パターニングして、CrSi
、0薄膜抵抗体の電極形成領域と第1層の^β電極との
上に配線電極を形成する工程を含むことを特徴とする方
法、および (イ)絶縁膜に電極形成用開口窓をあけたSi基板上に
、第1層のAIをスパッタリングし、パターニングして
、電極形成用開口窓と、形成すべきCrS+、0(Xは
1〜2の範囲の数を表す)薄膜抵抗体の2つの電極形成
領域とに、厚さ100〜5000人の第1層のl電極を
形成し、(ロ)第1層の^l電極表面に自然酸化されて
生成したA A 203薄層をRFエツチングにより除
去した後に、(ハ)CrS+、0をスパッタリングし、
パターニングして、2つの電極形成領域を跨ぐCr5i
xO薄膜抵抗体を形成し、(ニ)さらに5102換算6
0〜120 人の深さまでRFエツチングを行って、第
1層のAI!Itと、CrSi註薄膜抵抗体との表面に
、それぞれ自然酸化されて生成したA It 2i3 
とCr、0.との薄層を除去した後に、(ホ)第2層の
AIをスパッタリングし、パターニングして配線電極を
形成する上程を含むことを特徴とする方法によって解決
することができる。
Means for Solving Problem C] The above problem is a method for manufacturing a semiconductor device having a CrSi, 0 thin film resistor, which includes: (a) forming an 81 substrate t in which an opening window for forming an electrode is formed in an insulating film; , O (X represents a number in the range of 1 to 2) thin film was sputtered and patterned to form Cr51. D thin film resistor is formed, (b) 0.
After pretreatment with 5-5.0% HF, the first layer ^1 is sputtered and patterned to form the first layer ^1 on the opening window.
forming electrodes, (c) applying photosensitive polyimide, exposing, developing, and curing with heat to form a flattened interlayer insulating film;
Next, by selective etching, the electrode formation region of the CrSi,0 thin film resistor and the ^β electrode of the first layer were exposed, and (d) the Cr2O on the surface of the CrSi,0 thin film resistor, which was generated by natural oxidation, and A I 2 on the surface of the first layer ^l electrode.
After removing the thin layer of 03 by RF etching to a depth of 60 to 120 people in terms of 8102, (e) the second layer ^! CrSi is sputtered and patterned.
, a method characterized by including a step of forming a wiring electrode on the electrode formation region of the thin film resistor and the ^β electrode of the first layer, and (a) opening an opening window for electrode formation in the insulating film. The first layer of AI is sputtered and patterned on the Si substrate prepared to form an opening window for forming an electrode, and a CrS+,0 (X represents a number in the range of 1 to 2) thin film resistor to be formed. A first layer of 100 to 5,000 electrodes with a thickness of 100 to 5,000 people is formed in each of the two electrode formation regions, and (b) a thin layer of A A 203 that is naturally oxidized and generated on the surface of the first layer ^l electrode is RF etched. (c) sputtering CrS+,0,
Cr5i is patterned to straddle the two electrode formation regions.
xO thin film resistor is formed, (d) further 5102 conversion 6
Perform RF etching to a depth of 0 to 120 people and create the first layer of AI! A It 2i3 generated by natural oxidation on the surfaces of It and CrSi thin film resistor, respectively.
and Cr, 0. This problem can be solved by a method characterized by including the steps of (e) sputtering and patterning a second layer of AI to form a wiring electrode after removing a thin layer of the same.

〔作 用〕[For production]

第1の発明の方法は、絶縁膜の上にまずCrS+XO薄
膜抵抗体を形成し、この上に第2層の・^l配線電極を
形成する。第2の発明の方法は、絶縁膜の上に形成すべ
きCr 31x O薄膜抵抗体の2つの電極形成領域に
、まず2つの第1層のl電極を形成し、次にこれらを跨
ぐCrSi、0薄膜抵抗体を形成した上に、この電極形
成領域に第2層の^l配線電極を形成する。
In the method of the first invention, a CrS+XO thin film resistor is first formed on an insulating film, and a second layer of wiring electrodes is formed on this. The method of the second invention first forms two first layer l electrodes in two electrode formation regions of a Cr 31x O thin film resistor to be formed on an insulating film, and then CrSi, which straddles these, In addition to forming the 0 thin film resistor, a second layer ^l wiring electrode is formed in this electrode formation region.

RFエツチングによる自然酸化物の除去は、第1の発明
の方法では1回ですむが、これに対して第2の発明の方
法では2回の除去を必要とする。
The method of the first invention requires removal of the native oxide by RF etching once, whereas the method of the second invention requires removal twice.

しかし第2の発明ではCrS+、0薄膜抵抗体を第1層
と第2層とのAl電極で挟持する形となるので、機械的
強度が大きい利点を有する。
However, in the second invention, since the CrS+,0 thin film resistor is sandwiched between the Al electrodes of the first layer and the second layer, it has the advantage of high mechanical strength.

なお、いずれの発明の方法においても、絶縁膜の電極形
成用開口窓には、RFエツチングの前に第1のAl電極
が形成されているので、酸化物除去のRFエツチングが
開口を通してバルクSiに達してダメージを与えること
はない。
Note that in both methods of the invention, the first Al electrode is formed in the opening window for electrode formation in the insulating film before RF etching, so that the RF etching for oxide removal is applied to the bulk Si through the opening. It will not reach you and cause any damage.

CrSi、O薄膜抵抗体の表面に自然酸化されて生成し
たCr、O,薄層のRFエツチングは、S10□に換算
して60〜120人の深さとすることが必要であり、6
0人より薄いと酸化物の除去が十分でなく、120人よ
り深いと、厚さ200人程度の薄膜抵抗体にダメージを
与える恐れがある。
RF etching of the thin layer of Cr, O, produced by natural oxidation on the surface of the CrSi, O thin film resistor needs to have a depth of 60 to 120 people in terms of S10□.
If it is thinner than 0, the removal of oxide will not be sufficient, and if it is deeper than 120, the thin film resistor, which is about 200, may be damaged.

電極形成用開口窓をあけた絶縁膜は、窓の底に露出して
いるバルクSiが自然酸化されて5102の薄層となっ
ているので、0.5〜5.0%HFで除去する。HFの
濃度が0.5%より低いと、SiO□の除去は十分でな
く、5.0%より高いときはCrSi註を溶解しないが
、酸化絶縁膜にダメージを与える。
In the insulating film with the opening window for electrode formation, the bulk Si exposed at the bottom of the window is naturally oxidized and becomes a thin layer of 5102, so it is removed with 0.5 to 5.0% HF. When the concentration of HF is lower than 0.5%, the removal of SiO□ is not sufficient, and when it is higher than 5.0%, it does not dissolve the CrSi but damages the oxide insulating film.

なお、第1の発明の方法は、層間絶縁膜として、感光性
ポリイミドを使用するので、従来のCVDによるPSG
とは異なり、平坦化工程を簡略化することができる。も
ちろん、これを第2の発明に適用することもできる。
Note that the method of the first invention uses photosensitive polyimide as the interlayer insulating film, so PSG by conventional CVD is not used.
In contrast, the planarization process can be simplified. Of course, this can also be applied to the second invention.

CrSi、0薄膜抵抗体は厚さが通常20OA程度と極
tて薄いので、第2の発明の方法は、第1層のAl電極
の上にこの薄膜を被着したとき、段差で膜切れを生じ易
い。これを防ぐために第1層のl膜の厚さを100〜5
000 Aとして段差を小さくすることが必要である。
Since the CrSi,0 thin film resistor is extremely thin, usually about 20 OA, the method of the second invention prevents film breakage due to steps when this thin film is deposited on the first layer of Al electrode. Easy to occur. In order to prevent this, the thickness of the first layer L film is 100~5.
000 A, it is necessary to reduce the level difference.

〔実施例〕〔Example〕

実施例1 第1の発明の方法の実施態様として、第1図に示すSi
基板lは厚さ4000人の酸化絶縁膜2を有し、これに
電極形成用開口窓3をあけ、9 mTorrのAr中で
0.7kWの出力でCrSi。Dを20間分スパッタリ
ングして厚さ200人の薄膜を被着し、選択的反応性イ
オンエツチングにより開口窓3をNaさせ、薄膜抵抗体
4を形成した(a)。
Example 1 As an embodiment of the method of the first invention, the Si
The substrate 1 has an oxide insulating film 2 with a thickness of 4000 nm, an opening window 3 for forming an electrode is formed in this, and CrSi is deposited at a power of 0.7 kW in Ar at 9 mTorr. A thin film having a thickness of 200 mm was deposited by sputtering D for 20 minutes, and the opening window 3 was etched with Na by selective reactive ion etching to form a thin film resistor 4 (a).

次に、1.0%HFで10秒間前処理して、開口窓3の
底に自然酸化によって生成した5in2薄層を除去した
後に、lQmTorrのAr中で3.QkWの出方でス
パッタリングして厚さ9000人のAl膜を被着し、5
0℃の)13P[11,で選択的ウェットエツチングを
行って、第1層のAl電極5を形成した(b)。
Next, after pretreatment with 1.0% HF for 10 seconds to remove the 5in2 thin layer generated by natural oxidation at the bottom of the aperture window 3, 3. A 9,000-layer thick Al film was deposited by sputtering at the output of QkW, and 5
Selective wet etching was performed using 13P[11, 0° C.] to form the first layer of Al electrode 5 (b).

感光性ポリイミド6を、常法によって塗布し、露光・現
像して、熱硬化した後に選択的エツチングして、A!電
極5と、抵抗体の上に形成すべき2つの電極領域7とを
露出させた(C)。
Photosensitive polyimide 6 was coated by a conventional method, exposed to light, developed, thermally cured, and then selectively etched to form A! The electrode 5 and the two electrode regions 7 to be formed on the resistor were exposed (C).

8mTorrのAr中で13.5MHz 、 0.8k
Wの出力で5in2に換算して深さが100Aとなるよ
うにRFエツチングを行って、Ar電極5表面の自然酸
化^1203薄層とCr51.ON膜抵抗体4表面の自
然酸化Cr、03 とを薄層を除去した後に、(b)と
同じ条件で厚さ1.51!Iaのl膜を被着し、パター
ニングして、第2層の配線電極8.8′を形成した(d
)。
13.5MHz in 8mTorr Ar, 0.8k
RF etching is performed so that the depth becomes 100A when converted to 5in2 with the output of W, and the thin layer of natural oxidation^1203 and the Cr51. After removing a thin layer of naturally oxidized Cr, 03 on the surface of the ON film resistor 4, the thickness was reduced to 1.51 cm under the same conditions as in (b). A film of Ia was deposited and patterned to form a second layer wiring electrode 8.8' (d
).

C’rSi、0薄膜抵抗体−A1電極の接触面積16X
6μ2についての接触抵抗は10mΩであった。
C'rSi,0 thin film resistor-A1 electrode contact area 16X
The contact resistance for 6 μ2 was 10 mΩ.

実施例2 第2の発明の方法の実施態様として、第2図に示す81
基板は厚さ4000人の酸化絶縁膜2を有し、電極形成
用開口窓3をあけ、1.0%HFで10秒間前処理して
、開口窓3の底に自然酸化によって生成したSiO,薄
層を除去した後にlQmTorrのAr中で3kWの出
力でスパッタリングして厚さ1000への^1薄膜を被
着し、50℃のH,PD、で選択的エツチングして、バ
ルクSiの上の第1層のAIl電極と、形成すべきCr
Si。0薄膜抵抗体4の下の第1層のAI!電極5とを
形成した(a)。
Example 2 As an embodiment of the method of the second invention, 81 shown in FIG.
The substrate has an oxide insulating film 2 with a thickness of 4,000 nm, an opening window 3 for forming an electrode is opened, and pre-treatment with 1.0% HF is performed for 10 seconds. After removing the thin layer, deposit a ^1 thin film to a thickness of 1000 nm by sputtering in Ar at lQmTorr with a power of 3 kW and selectively etching with H, PD, at 50 °C to form a thin film on the bulk Si. First layer Al electrode and Cr to be formed
Si. 0 AI of the first layer under the thin film resistor 4! (a).

10mTorrOAr中で、13.5MHz 、1.0
kWの出力でRFエツチングして第1層の^l電極5.
5′の表面に自然酸化して生成した^n 、03薄層を
除去した後に、9 mTorrのAr中で0.7kWの
出力で20分間スパッタリングして厚さ200人のCr
S+、0薄膜を形成し、選択的反応性エツチングによっ
て薄膜抵抗体4をパターニングした(b)。
13.5MHz, 1.0 in 10mTorrOAr
5. The ^l electrode of the first layer is etched by RF etching with a power of kW.
After removing the thin layer of 03 produced by natural oxidation on the surface of 5', sputtering was performed for 20 minutes at a power of 0.7 kW in Ar at 9 mTorr to form a Cr layer with a thickness of 200 nm.
An S+,0 thin film was formed and a thin film resistor 4 was patterned by selective reactive etching (b).

さらに(b)と同様に、SiO□に換算して厚さ100
人までRFエツチングして、薄膜抵抗体4表面の自然酸
化Cr2D、薄層を除去した後に、(a)と同様にして
厚さ7000 Aの第2層のArを被着し、選択的エツ
チングにより第1層のAIl電極、5′に配線電極8.
8′を形成した(C)。
Furthermore, as in (b), the thickness is 100 in terms of SiO□.
After removing the naturally oxidized Cr2D and thin layer on the surface of the thin film resistor 4 by RF etching, a second layer of Ar with a thickness of 7000 A was deposited in the same manner as in (a), and by selective etching. 1st layer Al electrode, wiring electrode 5'.
8' was formed (C).

第1層のへβ電極が占める絶縁層の面積4×642につ
いてのCrSi、O薄膜抵抗体−A!電極の接触抵抗は
5mΩであった。
CrSi,O thin film resistor-A for the area of the insulating layer occupied by the β electrode of the first layer 4×642! The contact resistance of the electrode was 5 mΩ.

〔発明の効果〕〔Effect of the invention〕

本発明の方法による半導体装置はCr5IXO薄膜抵抗
体−Alt&極の接触抵抗が極めて小さい利点を有する
。その他RFエツチングで導体表面の酸化物を除去する
とき、開口窓を第1層のAIl電極塞いでいるので、8
1基板にダメージを与えることがなく、またAr配線の
形成は、薄膜抵抗体を形成した後に行うので、薄膜の選
択的エツチングによるl配線へのダメージもない。
The semiconductor device according to the method of the present invention has the advantage that the contact resistance between the Cr5IXO thin film resistor and the Alt&pole is extremely small. In addition, when removing oxides on the conductor surface by RF etching, the opening window is covered with the first layer of Al electrode, so 8
Since the Ar wiring is formed after forming the thin film resistor, there is no damage to the l wiring due to selective etching of the thin film.

さらに、第1の発明の方法は、平坦化層間絶縁膜を簡略
な工程で形成することができ、第2の発明の方法は、C
rSiイ0薄膜抵抗体が第1層と第2層とのlii極の
間に強固に挟持される特長を有する。
Furthermore, the method of the first invention can form a planarized interlayer insulating film in a simple process, and the method of the second invention can form a planarized interlayer insulating film in a simple process.
The rSi0 thin film resistor has the feature that it is firmly sandwiched between the lii poles of the first layer and the second layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は第1の発明の実施態様を示す工程図、第2図は
第2の発明の実施態様を示す工程図である。 1・・・81基板、     2・・酸化絶縁膜、3・
・・電極形成用開口窓、 4・・・CrS+、O薄膜抵抗体、 5・・・第1層のl電極、 6・・・平坦化層間絶縁膜、 7・・・抵抗体の電極形成領域、 8・8′・・・配線電極。
FIG. 1 is a process diagram showing an embodiment of the first invention, and FIG. 2 is a process diagram showing an embodiment of the second invention. 1...81 substrate, 2... oxide insulating film, 3...
... Opening window for electrode formation, 4... CrS+, O thin film resistor, 5... L electrode of first layer, 6... Flattening interlayer insulating film, 7... Electrode formation region of resistor , 8・8'... Wiring electrode.

Claims (1)

【特許請求の範囲】 1、薄膜抵抗体を有する半導体装置の製造方法であって
、 (イ)電極形成用開口窓をあけた保護膜を半導体基板上
に形成したのち、薄膜を該保護膜上にスパッタリングし
、パターニングして、薄膜抵抗体を形成し、 (ロ)第1層の電極材料をスパッタリングし、パターニ
ングして前記開口窓に第1層の電極を形成し、 (ハ)層間絶縁膜を形成し、次に選択的エッチングによ
り、薄膜抵抗体の電極形成領域と第1層の電極とを露出
させ、 (ニ)自然酸化されて生成した、薄膜抵抗体表面の酸化
膜をRFエッチングにより除去した後に、 (ホ)第2層の電極材料をスパッタリングし、パターニ
ングして、薄膜抵抗体の電極形成領域と第1層の電極と
の上に配線電極を形成する工程を含むことを特徴とする
半導体装置の製造方法。 2、薄膜抵抗体を有する半導体装置の製造方法であって
、 (イ)電極形成用開口窓をあけた保護膜を半導体基板上
に形成したのち、第1層の電極材料をスパッタリングし
、パターニングして、電極形成用開口窓に、第1層の電
極を形成し、 (ロ)薄膜をスパッタリングし、パターニングして、薄
膜抵抗体を形成し、 (ハ)さらにRFエッチングを行って、薄膜抵抗体の表
面に形成された自然酸化膜を除去した後に、 (ニ)第2層の電極材料をスパッタリングし、パターニ
ングして配線電極を形成する工程を含むことを特徴とす
る半導体装置の方法。
[Claims] 1. A method for manufacturing a semiconductor device having a thin film resistor, which comprises: (a) forming a protective film with openings for electrode formation on a semiconductor substrate; and then depositing a thin film on the protective film. sputtering and patterning to form a thin film resistor; (b) sputtering and patterning a first layer electrode material to form a first layer electrode in the opening window; (c) an interlayer insulating film. Then, selective etching is performed to expose the electrode formation region of the thin film resistor and the first layer electrode, and (d) the oxide film on the surface of the thin film resistor, which is generated by natural oxidation, is removed by RF etching. After the removal, the second layer electrode material is sputtered and patterned to form a wiring electrode on the electrode formation region of the thin film resistor and the first layer electrode. A method for manufacturing a semiconductor device. 2. A method for manufacturing a semiconductor device having a thin film resistor, comprising: (a) forming a protective film with openings for electrode formation on a semiconductor substrate, and then sputtering and patterning a first layer of electrode material; Then, a first layer of electrode is formed in the opening window for electrode formation, (b) the thin film is sputtered and patterned to form a thin film resistor, (c) further RF etching is performed to form the thin film resistor. A method for a semiconductor device, comprising the steps of: (d) sputtering and patterning a second layer electrode material to form a wiring electrode after removing a natural oxide film formed on the surface of the semiconductor device.
JP14851090A 1990-06-08 1990-06-08 Manufacture of semiconductor device Pending JPH0444260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14851090A JPH0444260A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14851090A JPH0444260A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0444260A true JPH0444260A (en) 1992-02-14

Family

ID=15454382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14851090A Pending JPH0444260A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0444260A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989970A (en) * 1994-06-08 1999-11-23 Nippondenso Co., Ltd. Method for fabricating semiconductor device having thin-film resistor
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
JP2005235888A (en) * 2004-02-18 2005-09-02 Ricoh Co Ltd Semiconductor device and manufacturing method thereof
JP2010177506A (en) * 2009-01-30 2010-08-12 Nec Corp Wiring board, and method of manufacturing the same
WO2010119839A1 (en) 2009-04-15 2010-10-21 株式会社 アマダ Punch die and method of supplying lubricating oil

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989970A (en) * 1994-06-08 1999-11-23 Nippondenso Co., Ltd. Method for fabricating semiconductor device having thin-film resistor
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
JP2005235888A (en) * 2004-02-18 2005-09-02 Ricoh Co Ltd Semiconductor device and manufacturing method thereof
JP2010177506A (en) * 2009-01-30 2010-08-12 Nec Corp Wiring board, and method of manufacturing the same
WO2010119839A1 (en) 2009-04-15 2010-10-21 株式会社 アマダ Punch die and method of supplying lubricating oil
US9669450B2 (en) 2009-04-15 2017-06-06 Amada Company, Limited Punch tool device and method of supplying lubricating oil

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