JPH0444410A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To reduce the number of arithmetic processing stages and to decrease the processing time by adopting the filter circuit with 2 stages (1st and 2nd stages) and omitting the data processing for a data in which a filter coefficient is '0'. CONSTITUTION:A 1st stage 6 consists of data delay devices 3a, 3c - 3o connected sequentially in series, filter coefficient ROMs a,c-o coupled respectively with the output of the delay device 3a, 3c - 3o and an adder circuit 4. A 2nd stage 7 consists of a filter coefficient ROMh coupled with a central delay 3i. The output sides of the 1st stage 6 and the 2nd stage 7 are connected to the input side of a selector 8 and the output signal from both the stages is outputted from an output terminal 5 alternately for each 1/2t1.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an oversampling type digital filter circuit for audio bands (CD, DAT, BS, etc.).

"Prior art" When the cutoff frequency is near the Nyquist frequency,
As shown in FIG. 2, the impulse response of the filter is that, except for the center (maximum value point h), data that is approximately O is obtained at every other sampling point.

Appears in f + je 6 y n.

However, in the conventional digital filter that performs oversampling processing, as shown in FIG. ) (3b)～(
3o). These data delayers (3a)
The outputs of (3b) to (3o) are the corresponding filter coefficients in the filter coefficient ROM (a) (b) to (0) that store the filter coefficients of each point up to a''-'o in Fig. 2, respectively. After being multiplied, the signals are sent to an adder circuit (4) for addition, and are output from an output terminal (5).

[Problems to be solved by the invention] In conventional circuits, the filter coefficients for each point from a to 0 were stored and processed in their own ROMs.
The problem is that not only the number of processes increases, but also the processing time becomes longer.

The present invention reduces the capacity of the filter coefficient ROM.

Another object of the present invention is to obtain a digital filter circuit with short processing time.

[Means for Solving the Problems] The present invention provides an oversampling type digital filter circuit for processing digital signals when the cutoff frequency is near the Nyquist frequency.
The first stage includes a first stage that processes data near the maximum value or minimum value for each sampling point, and a second stage that processes approximately O data that appears for each sampling point, and the first stage processes data near the maximum value or minimum value for each sampling point. Each delay device is connected in series, a filter coefficient ROM is connected to the output side of each delay device, and these filter coefficient ROMs are connected to an adder circuit.

The second stage is formed by coupling a maximum value filter coefficient ROM to the output side of the central delay device among the delay devices, and alternately connects the output side of the first stage and the output side of the second stage. It is connected to a selector for switching output.

"Operation" Data near the maximum value or minimum value for each sampling point is multiplied by each filter coefficient ROM and processed by the adder circuit. Approximately 0 that appears at every sampling point
Since the data of is not sent to the selectors except for the central delay device, processing of the filter coefficient O is not substantially performed.Only the maximum value output of the central delay device is the filter coefficient R of the maximum value.
It is multiplied by OM and sent to the selector. Since the selector alternately switches and outputs between the first stage and the second stage, the second stage outputs 0 except for the maximum value at the center, and the calculation processing is approximately halved.

"Example" An embodiment of the present invention will be described below with reference to FIG.

(1) is a digital data input terminal, and this input terminal (1) is coupled to the first stage (6) and the second stage (7). Among these, the first stage (6) is a data delay device (3a) (3c) to (3) connected in series.
0) and these delay devices (3a) (3c) ~(3o
) respectively coupled to the output side of the filter coefficient ROM
(a) Consists of (c) to (,) and an adder circuit (4).

Each delay time of the delay devices (3a) (3c) to (30) is between one sampling point (t,) in FIG.
The coefficients of the filter coefficient circuits (a), (c) to (0) correspond to a, c, e, g, i, m, and o in FIG. 2, respectively.

The second stage (7) consists of a filter coefficient RoM(h) coupled to the central delayer (31), and the coefficients of this filter coefficient ROM(h) shall correspond to h in FIG. .

The output sides of the first stage (6) and the second stage (7) are coupled to the input side of the selector (8), and the output terminal (5)
From then on, the signals are output alternately every +t1.

In the above configuration, the selector (8) is a + Ct e r g e l e k g in FIG.
The first stage (6) at time at each point of m g O
b + d e f in Fig. 2
It switches to the second stage (7) side at each point e b t j * l e n. Therefore, a g Q
The data of each point of g e g g y l g k 1 mHO is outputted via the selector (8). Also, b,
d, f.

Since the data at each point of h e J e l v n is input O to the selector (8), there is no output. However, only the data at point h is input to the selector (8) via the filter coefficient ROM (h). Then, the data is output from the selector (8).

"Effects of the Invention" As described above, the present invention has a two-stage configuration of the first stage and the second stage, and data processing with a filter coefficient of 0 is omitted, so the number of arithmetic operations is reduced and the processing time is reduced. Becomes shorter. Furthermore, the number of filter coefficient ROMs can be reduced to approximately half, and the circuit can be simplified. Furthermore, in the conventional circuit, a zero value insertion circuit is inserted after data input, so the clock rate doubles, but in the present invention, the clock rate does not change until the selector input.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter circuit according to the present invention, FIG. 2 is an explanatory diagram of filter coefficients when the cutoff frequency is near the Nyquist frequency,
FIG. 3 is a block diagram of a conventional digital filter circuit. (1)...Input terminal, (2)...0 value insertion circuit, (
3a) (3c) to (30)...data delay device, (4)
... Addition circuit, (5) ... Output terminal, (6) ...
1st stage, (7)...2nd stage. (8)...Selector. Applicant: Fujitsu General Co., Ltd.

Claims (1)

[Claims] (1) In an oversampling type digital filter circuit that processes a digital signal when the cutoff frequency is near the Nyquist frequency, a first stage that processes data near the maximum value or minimum value for each sampling point; and a second stage that processes approximately 0 data that appears at each sampling point, and the first stage connects delay devices for each sampling point in series, and a filter coefficient ROM is provided on the output side of each delay device. and these filter coefficients R
OM is coupled to an adder circuit, and the second stage is composed of a maximum value filter coefficient ROM coupled to the output side of the central delay device among the delay devices, and the output side of the first stage and the first stage are coupled to the output side of the central delay device. A digital filter circuit characterized in that the output sides of two stages are coupled to a selector that alternately switches and outputs.