JPH0444416A - Change point detecting circuit - Google Patents

Abstract

PURPOSE:To realize this circuit through the employment of two data latch circuits only corresponding to a digital signal source by providing a logic circuit delaying an input digital signal by a predetermined time so as to output a detection signal representing a level change in the digital signal on the detection circuit. CONSTITUTION:When the level of a digital signal source 1 falls down, the output level of an inverter 11 rises, a data latch circuit (DL) 3 latches the high level of its D input and its output Q goes to a high level. With the output Q of the DL 3 set to a high level, the output of an OR circuit (OR) 7 goes to a high level and the output Q of a DL 8 goes to a high level synchronously with the rise of a detection clock signal. Similarly, when the digital signal source 1 rises, a DL 4 latches a high level, when a digital signal source 2 falls down, a DL 5 latches a high level, and when the digital signal source 2 rises,a DL 6 latches a high level and the processing is implemented similarly with the above-mentioned operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital circuit, and more particularly to a detection circuit for detecting a point of change in signal level.

(Prior Art) FIG. 3 shows a conventional digital signal level change point detection circuit.

In FIG. 3, digital signal source 1 is connected to inverter II
It is connected to the rising edge detecting circuit 13 via the rising edge detecting circuit 13 and directly to the rising edge detecting circuit 14. Similarly, the digital signal source 2 is connected to the rise detection circuit 15 via the inverter 12 and directly connected to the rise pressure detection port #81.
6. The rise detection circuits 13 to 16 are connected to a logic circuit 17.

The rising edge detection circuit 13Vi includes data latte circuits (D-flip-flops) 21 and n and an AND circuit n, and the data launch circuits 21 and 21)K are provided with a detection clock. Note that the rise detection circuits 14 to 16
The rising edge detection circuit 13 is also configured similarly to the rising edge detection circuit 13.

In the changing point detection circuit shown in FIG. 15 and 16 detect the change point of the digital signal from the digital signal source 2. The change point detection outputs from the rising edge detectors 13 to 16 are obtained as detector outputs via an OR circuit 17.

In this way, conventional change point detection circuits use two rising edge detection circuits per signal source, and detect the changing point of a digital signal by ORing the outputs of each rising edge detection circuit. There is.

(Problems to be Solved by the Invention) In the case of a conventional digital signal level change point detection circuit, a rise detection circuit is required depending on the number of signal sources to be detected. For this reason, not only does the number of constituent elements of the change point detection circuit itself increase.

Since the number of data latch circuits to which the detection clock is input increases, the load on the clock signal increases, causing problems such as an increase in delay time and a rounded clock.

Means for Solving Problem C) According to the present invention, a digital signal having first and second levels is input, and a first level signal is detected and a first level signal is sent out. a second latch circuit that detects the first latch circuit and the second level and sends out a second level signal;

a logic circuit that receives the first and second level signals, delays them by a predetermined time, and outputs a detection signal indicating a level change of the digital signal; A change point detection circuit characterized in that it includes a second latch circuit is obtained.

(Example) Next, the present invention will be explained with reference to examples.

Here, the description will be made assuming that there are two digital signal sources and the detection signal output time is one clock length of the detection clock signal.

Referring to FIGS. 1 and 2, when the level of digital signal source 1 falls (becomes low level), the output level of inverter (INV) 11 rises (high level), and data latch circuit (DL) 3 latches the high level of the D input, and as a result, the output Q becomes high level.

At this time, DL4. DL5. Each output Q of DL6 remains at low level. When the output Q of DL3 becomes high level, the output of the logical sum circuit (OR) 7 becomes high level, and the output Q of DL8 becomes high level in synchronization with the rise of the detection clock signal. At this time, the output Q of DL8 becomes low level, clearing DL3, and setting the output Q of DL3 to low level.

This causes the output of OR7 to become low level.

DL8 in synchronization with the rise of the next detection clock signal.
The output Q becomes low level, the output Q becomes high level, and the series of operations ends.

Similarly, when digital signal source 1 rises, DL4. DL if digital signal source 2 falls
5. When the digital signal source 2 rises, the DL6 latches the high level -y, and thereafter operates in the same manner as described above.

In this way, since only two data latch circuits are used for each digital signal source, the number of components can be reduced compared to conventional methods, and the detection clock is only used for one data latch circuit. Therefore, the load on the detection clock is constant.

(Effects of the Invention) As explained above, in the present invention, when detecting changes in signal levels of a plurality of digital signal sources, only two data latte circuits are used corresponding to the digital signal sources. The number of circuit elements can be reduced compared to the conventional one. Another advantage is that the load on the detection clock remains constant regardless of the number of digital signal sources.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a change point detection circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of the change point detection circuit shown in FIG. 1. FIG. 3 is a diagram showing a conventional change point detection circuit. 3, 4.5.6.8 is the data latch circuit (DL) 7 is the OR circuit 11.12 is the inverter (INv) 13, 1
4.15.16 is a rising edge detection circuit, 17 is an OR circuit, 21.22 is a data latch circuit, and n is an AND circuit. high level

Claims (1)

[Claims] 1 A first latch circuit receives a digital signal having first and second levels, detects the first level and sends out a first level signal, and detects the second level; a second latch circuit that sends out a second level signal; and a logic that receives the first and second level signals, delays them for a predetermined time, and outputs a detection signal indicating a level change in the digital signal. A change point detection circuit comprising: a change point detection circuit, wherein the first and second latch circuits are provided in correspondence with the number of digital signals.