JPH0444419B2 - - Google Patents

Info

Publication number
JPH0444419B2
JPH0444419B2 JP58243951A JP24395183A JPH0444419B2 JP H0444419 B2 JPH0444419 B2 JP H0444419B2 JP 58243951 A JP58243951 A JP 58243951A JP 24395183 A JP24395183 A JP 24395183A JP H0444419 B2 JPH0444419 B2 JP H0444419B2
Authority
JP
Japan
Prior art keywords
substrate
multilayer wiring
sic
wiring substrate
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58243951A
Other languages
Japanese (ja)
Other versions
JPS60136320A (en
Inventor
Hiroaki Doi
Tatsuji Sakamoto
Toshihiro Yamada
Motohiro Sato
Kanji Ootsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58243951A priority Critical patent/JPS60136320A/en
Publication of JPS60136320A publication Critical patent/JPS60136320A/en
Publication of JPH0444419B2 publication Critical patent/JPH0444419B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive improving heat dissipation capability by making an insulation substrate with heat-conductive material, heaping up the heat-conductive material and metal wiring material mutually for diffused junction and connecting to a conductor electrically. CONSTITUTION:An SiC substrate 2 wherein Al 1 is filled in a penetrated hole is made diffused junction with an Al wiring 3 and forms a multilayer wiring substrate. On the under surface of the multilayer wiring substrate, a lead wire 4 is attached and on the upper surface, an Si chip 6 is connected with solder 5. A cap 8 is attached to the multilayer wiring substrate with low melting point glass 7. The multilayer wiring substrate which has finished diffused junction has minute crevices which are nearly equal to the thickness of a wiring conductor and has effect of increasing the heat dissipation area of the SiC at the time of forced cooling.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は絶縁基板に複数のSiチツプが実装され
た半導体装置、特に発熱量の多いSiチツプの放熱
に好適な半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device in which a plurality of Si chips are mounted on an insulating substrate, and particularly to a semiconductor device suitable for dissipating heat from Si chips that generate a large amount of heat.

〔発明の背景〕[Background of the invention]

従来のこの種の半導体装置においては、例えば
特開昭57−2591号に開示されているようにアルミ
ナセラミツク基板（AI2O3板）にＷなどの配線を
施している。このAI2O3基板の熱伝導率は小さい
ため、発熱量の多い半導体素子を接続すると放熱
が不十分となるという欠点があつた。 In a conventional semiconductor device of this type, wiring made of W or the like is provided on an alumina ceramic substrate (AI 2 O 3 board), as disclosed in, for example, Japanese Patent Laid-Open No. 57-2591. Since the thermal conductivity of this AI 2 O 3 substrate is low, it has the disadvantage that heat dissipation is insufficient when semiconductor elements that generate a large amount of heat are connected to it.

〔発明の目的〕[Purpose of the invention]

本発明の目的は放熱性能の高い半導体装置を提
供することにある。 An object of the present invention is to provide a semiconductor device with high heat dissipation performance.

〔発明の概要〕[Summary of the invention]

炭化ケイ素（SiCと略す）は熱伝導率
（0.65cal／cm・sec・℃）が高い絶縁材料である
という点から放熱性能の高い多層配線基板材料に
適していると考えられてきた。しかし、SiC上に
従来の方法によつてＷメタライズなどの配線導体
を作成しようとすると、配線導体がはがれてしま
うため、SiCを用いた半導体装置は作られていな
い。 Silicon carbide (abbreviated as SiC) is an insulating material with high thermal conductivity (0.65 cal/cm・sec・℃), and has been considered suitable as a material for multilayer wiring boards with high heat dissipation performance. However, if an attempt is made to create a wiring conductor such as W metallization on SiC using a conventional method, the wiring conductor will peel off, so no semiconductor device has been manufactured using SiC.

そこで本発明者らは、鋭意検討した結果SiCへ
の配線導体作成法として配線導体をSiCへ拡散接
合することを試みた。 As a result of intensive study, the present inventors attempted diffusion bonding of a wiring conductor to SiC as a method for creating a wiring conductor to SiC.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の半導体装置の実施例を第１図、
第２図により説明する。第１図は断面図、第２図
は第１図のキヤツプを取り除いたものの平面図で
ある。第１図において貫通孔内に導体であるAl
１を入れられたSiC基板２はAlの金属配線杆３と
拡散接合され多層配線基板を形成している。この
多層配線基板の下面にはリード線４が付けられ、
上面にははんだ５を介してSiチツプ６が接合され
ている。多層配線基板には低融点ガラス７によつ
てキヤツプ８が取付けられている。第１図におい
て、配線導体はAl以外にも、SiC基板２と拡散接
合が可能で、電気抵抗の小さい金属であれば良
い。又、貫通孔内に入れる材料はAl以外にも、
貫通孔に充てん可能で電気抵抗の小さい金属であ
ればよい。なお、配線導体をSiC２に接合する場
合、配線導体は基板全面に渡り一体パターン加工
を施したものを用いる場合と部分パターン加工を
施したものを用いる場合がある。又、配線導体を
エツチングにより形成してもよい。拡散接合を完
了した多層基板には配線導体の厚さにほぼ等しい
微小隙間ができるため、強制空冷時にSiCの放熱
面積を増加させる効果がある。 Embodiments of the semiconductor device of the present invention will be described below with reference to FIG.
This will be explained with reference to FIG. FIG. 1 is a sectional view, and FIG. 2 is a plan view of the device shown in FIG. 1 with the cap removed. In Figure 1, there is Al as a conductor inside the through hole.
The SiC substrate 2 filled with 1 is diffusion bonded to an Al metal wiring rod 3 to form a multilayer wiring board. Lead wires 4 are attached to the bottom surface of this multilayer wiring board,
A Si chip 6 is bonded to the top surface via solder 5. A cap 8 is attached to the multilayer wiring board with a low melting point glass 7. In FIG. 1, the wiring conductor may be any metal other than Al, as long as it can be diffusion bonded to the SiC substrate 2 and has low electrical resistance. In addition to Al, the material to be inserted into the through hole is
Any metal can be used as long as it can be filled into the through hole and has low electrical resistance. Note that when bonding a wiring conductor to the SiC 2, the wiring conductor may be one that has been subjected to integral pattern processing over the entire surface of the substrate, or one that has been partially patterned. Alternatively, the wiring conductor may be formed by etching. After diffusion bonding, a micro gap approximately equal to the thickness of the wiring conductor is created in the multilayer board, which has the effect of increasing the heat dissipation area of SiC during forced air cooling.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、Siチツプを熱伝導率の大きい
材料に拡散接合ができるので、放熱性能の高い半
導体装置を得ることができる。 According to the present invention, since a Si chip can be diffusion bonded to a material with high thermal conductivity, a semiconductor device with high heat dissipation performance can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の半導体装置一実施例の断面
図、第２図は第１図においてキヤツプを いたも
のの平面図である。 １……Al、２……SiC、３……Al配線、４……
リード線、５……はんだ、６……Siチツプ、７…
…低融点ガラス、８……キヤツプ。 FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 with the cap removed. 1...Al, 2...SiC, 3...Al wiring, 4...
Lead wire, 5...Solder, 6...Si chip, 7...
...Low melting point glass, 8...Cap.

Claims (1)

【特許請求の範囲】[Claims] １ 内部に導体１を有する絶縁基板２上にSiチツ
プ６を実装した半導体装置において、前記絶縁基
板を熱伝導性材料により構成すると共に、この熱
伝導性材料と金属配線材３を相互に重ね合わせて
拡散接合し、前記金属配線材を前記導体と電気的
に接合したことを特徴とする半導体装置。1 In a semiconductor device in which a Si chip 6 is mounted on an insulating substrate 2 having a conductor 1 inside, the insulating substrate is made of a thermally conductive material, and the thermally conductive material and the metal wiring material 3 are superimposed on each other. A semiconductor device characterized in that the metal wiring material is electrically bonded to the conductor by diffusion bonding.
JP58243951A 1983-12-26 1983-12-26 Semiconductor device Granted JPS60136320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58243951A JPS60136320A (en) 1983-12-26 1983-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58243951A JPS60136320A (en) 1983-12-26 1983-12-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60136320A JPS60136320A (en) 1985-07-19
JPH0444419B2 true JPH0444419B2 (en) 1992-07-21

Family

ID=17111459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58243951A Granted JPS60136320A (en) 1983-12-26 1983-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60136320A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2556881B2 (en) * 1988-05-31 1996-11-27 キヤノン株式会社 Electric circuit device

Also Published As

Publication number Publication date
JPS60136320A (en) 1985-07-19

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