JPH044442A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the content of a cache memory from being updated by arbitrary data which are transferred between a main memory and CPU by providing a switching means which is opened and closed under the control from the CPU between the CPU and main memory. CONSTITUTION:When a CPU 1 requests data and makes a cache hit, the data exist in a cache memory 3 and the data are read. In case the cache hit is made wrongly, the CPU 1 accesses a main memory 2 and reads out the data and, at the same time, the data are written in the memory 3 along with the address. At the time of writing the data, old data in the memory 3 are updated. On the other hand, the CPU 1 closes (conducts) a switching means 3f. Therefore, data can be transferred directly between the CPU 1 and main memory 2 and updating of the cache memory 3 can be stopped unconditionally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus having a cache memory (main memory buffer) between a main memory and a central processing unit.

[Conventional technology]

FIG. 2 is a schematic configuration diagram of a storage device having a conventional cache memory. In the figure, 1 is the central processing unit (C
PU), 2 is a main memory, 3 is a cache memory (main memory buffer) for buffering data exchange and passing operations between the central processing unit 1 and the main memory 2, and 3a is a main memory in the cache memory. Address array 3b stores addresses of held data; 3b is a comparator that determines whether data requested by the CPUI is stored in the cache memory; 3c stores data held in the cache memory. Data array, 3d is central processing unit 1, main memory 2 and cache memory 3
3e is an address bus for passing the address part of the data to be passed between the central processing unit 1 and the main storage device 2 and the cache memory 3; 4 is a cache memory bus that connects the central processing unit 1 and the cache memory 3, and 5 is a memory bus that connects the main storage device 2 and the cache memory 3.

Next, the operation will be explained. In cache memory 3,
Initially, no data is stored. When data is received and passed between the central processing unit 1 and the main memory 2, the address bus 3d is monitored within the cache memory 3 and the address corresponding to the data is stored in the address array 3a.
Store in. At the same time, the hit comparator 3b compares the data at this address with the contents of the address array 3a, and determines that the data at the corresponding address is not stored in the address array 3a (hit miss).

Then, the above data is passed through the data bus 3e to the data array 3c, and data at the corresponding address is simultaneously stored in the address array 3a.

In this way, when data is received and passed between the central processing unit I and the main memory 2, the human comparator 3
Based on the determination b, each piece of data is stored in the address array 3a and data array 3c one after another.

If there is no data in the cache memory 3, writing is performed unilaterally, and if the old address and data have already been stored, the new receiver updates the old data in a predetermined order with the transferred data.

[Problem to be solved by the invention]

In devices using conventional cache memory, the data in the cache memory is uniformly updated for data that has been received or passed in the past, so it is expected that it will not be used again in the near future. This will reduce the efficiency of the memory usage if the data that is sent is received or passed.Furthermore, if you simply try to transfer data from one address space in main memory to another address space, Even in this case, there is a problem in that the data in the cache memory is easily updated by simply transferring data to and from the central processing unit.

This invention was made to solve the above-mentioned problems, and it is possible to prevent the contents of the cache memory from being updated by arbitrary data that is exchanged between the main memory and the central processing unit. The purpose of the present invention is to obtain a storage device that can prevent the contents of a cache memory from being changed by the transferred data when data is transferred from one address space to another address space in a main memory device. .

[Means to solve the problem]

In this invention, in order to solve the above problems, a cache memory 3 is provided between the central processing unit 1 and the main storage device 2.
In the information processing apparatus which transfers data between the central processing unit 1 and the main storage unit 2, a switching means 3f is provided between the central processing unit 1 and the main storage unit 2, which is opened and closed under control from the central processing unit 1.

[Effect]

When the central processing unit 1 requests and caches data, the data exists in the cache memory 3 and is read from there. In the case of a hit miss, the central processing unit 1 accesses the main memory 2 and reads the data, and the data is written to the cache memory 3 along with the address. At this time, old data in the cache memory is updated. On the other hand, by closing (conducting) the switch means 3f, the central processing unit 1 can directly transfer data between the central processing unit 1 and the main storage device 2, and can unconditionally stop updating the cache memory 3. can. Bypass control of the cache memory 3 is made such that data reception from the central processing unit 1 to the main storage device 2 is arbitrarily performed at the time of execution of transfer.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a configuration diagram of an information processing apparatus according to the present invention. In the figure, 1 is a central processing unit (CPU), 2 is a main memory, and 3 is a cache memory (main memory buffer) for buffering data receiving and passing operations between the central processing unit 1 and the main memory 2. 3a is an address array that stores addresses of data held in the cache memory; 3b is an address array that stores addresses of data held in the cache memory;
is a human comparator that determines whether the data requested by CPU1 is stored in the cache memory;
3c is a data array for storing data held in the cache memory; 3d is a data array for passing the address part of the data to be passed between the central processing unit 1, the main storage device 2, and the cache memory 3; address bus, 3
e is a data bus for receiving and passing data portions between the central processing unit 1 and the main storage device 2 and cache memory 3; 4 is a cache memory bus connecting the central processing unit 1 and the cache memory 3; , 5 is the main memory W2
This is a memory bus that connects the cache memory 3 and the cache memory 3.

Next, 3f is a bypass switch that is controlled by the central processing unit 1 and controls whether data transferred between the main storage devices 2 is stored in the cache memory or bypassed; A bypass bus 3h directly connects the data bus of the central processing unit 1 and the main storage device 2 when bypassing the data bus, and a bypass switch control line 3h is used by the central processing unit 1 to control the bypass switch 3f.

The bypass switch 3f has a bypass mode position where the cache memory bus 4 and the memory bus 5 are connected by opening and closing, and a normal mode position where the bypass switch 3f disconnects the cache memory bus 4 and the memory bus 5.

Next, the operation and effect will be explained. First, data exchanged between the central processing unit 1 and the main memory 2 is stored in the cache memory 3. At this time, the central processing unit 1
controls the bypass switch 3f to the normal mode position,
Data is received and passed. When the central processing unit 1 instructs to read data at a predetermined address, the comparator 3b of the cache memory 3 compares the data at this address with the contents of the address array 3a, and the data at the corresponding address is stored in the address array 3a. If it is determined that the data is not stored in the main memory 2, the data is read out from the main memory 2, and this data is simultaneously stored in the data array 3c via the data bus 3e, and the data at the corresponding address is stored in the address array 3a from the address bus 3d. . At this time, old data is removed from address array 3a and data array 3C, respectively, and the data is updated.

On the other hand, if the data passed between the central processing unit 1 and the main storage device 2 is not to be unconditionally stored in the cache memory, the cache memory bypass switch 3f is controlled to the bypass mode position. data is received and passed. At this time, when the central processing unit 1 attempts to read data from the main storage device 2, if the corresponding data is already stored in the cache memory 3 (matching is determined by the comparator 3b), this data will be read. It is also possible to read data from the data array 3c through the data bus 3e. Conversely, if the relevant data is not stored in the cache memory (mismatch), the data is directly transferred between the central processing unit 1 and the main storage device 2 through the switch 3f. At this time, storage of address data in the address array 3a is also prohibited.

For this reason, the address array 3a and the hit comparator 3b in the cache memory 3 always monitor the contents of the address bus 3d, but when the bypass mode to the cache memory is specified, the data read operation At this time, the contents of the address array 3a are not updated regardless of whether the addresses match or do not match.

Next, when writing data from the central processing unit 1 to the main memory 2, if the corresponding data is already stored in the cache memory, the corresponding data in the cache memory 3 is invalidated via the data bus 3e. can perform the following functions.

In the above embodiment, the bypass switch 3r and the bypass bus 3g are provided inside the cache memory 3, but the bypass switch 3f and the bypass bus 3g may be provided outside the cache memory 3. In addition, in the above embodiment, the cache memory 3 that is involved in receiving and passing data between the central processing unit 1 and the main storage unit 2 has been described, but an auxiliary storage unit provided separately from the main storage unit 2 and the central processing unit 1 has been described. , or may be involved in receiving and passing data to and from other input/output devices.

In addition, in the above embodiment, the cache memory connected between the central processing unit and the main storage device was explained.
When considering the function of transferring data from one address space in the main memory to another address space, a dedicated device for data transfer that can be controlled from the central processing unit is set up independently of the cache memory. The transfer data may be provided on the memory bus in such a manner that the transfer data is not stored in the cache memory. [Effects of the Invention] As explained above, according to the present invention, in an information processing device in which a cache memory is provided between a central processing unit and a main storage device and data is transferred between them, the central processing A switch means that is opened and closed under control from the device is provided between the central processing unit and the main memory, and the cache memory is bypassed by the switch means, thereby preventing unnecessary data from being stored in the cache memory. Since the configuration is configured to prevent the cache memory from being updated with unnecessary data inadvertently, the small capacity cache memory can be used effectively, making it possible to reduce the data storage area at low cost. In addition, there are effects such as the ability to improve the processing speed involved in receiving and passing data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an information processing apparatus having a cache memory according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing an information processing apparatus having a conventional cache memory. 1 is a central processing unit, 2 is a main memory, 3 is a cache memory, 3a is an address array, 3b is a comparator, 3
c is a data array, 3d is an address bus, 3e is a data bus, 3f is a bypass switch, 3g is a bypass bus,
3h indicates the Bay Ibas Isochi city 11 wholesale line, 4 indicates the cache memory bus, and 5 indicates the memory bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an information processing device in which a cache memory is provided between a central processing unit and a main storage device and data is transferred between the two, a switch means that is opened and closed under control from the central processing unit is connected between the central processing unit and the main storage device. An information processing device characterized in that it is provided between a main storage device.