JPH0444431B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a semiconductor device based on a novel construction principle. Conventionally, a pn junction, which is a main part of a semiconductor device, has been made by a diffusion method, an alloy method, an ion implantation method, a growth junction formation method, or the like. However, in all of the pn junctions created by these methods, the impurity concentration is statistically distributed and continuously changes spatially. For this reason, when attempting to miniaturize semiconductor elements, for example, there are physical limits due to the statistical distribution of this impurity concentration. In the present invention, when adding impurities into a semiconductor layer,
By controlling impurity atoms in units of monoatomic layers and localizing impurities in predetermined regions within the semiconductor layer,
It is an object of the present invention to provide a semiconductor device having characteristics that cannot be achieved by conventional methods. The present invention is a semiconductor device configured using a semiconductor material as a base material, and has an impurity region in which impurities are limited in a monoatomic layer or a thin layer similar thereto as an impurity region introduced into the base material. It has characteristics. This structure was only realized with the development of molecular beam epitaxial method. Since the semiconductor device of the present invention has the characteristic semiconductor stacked structure as described above, it is possible to realize a semiconductor device having various characteristic characteristics that could not be realized with conventional semiconductor devices. Note that impurities are usually introduced in a single atomic layer or in a single or multiple layers that are equal to or thinner than the depletion layer in a semiconductor device that includes a depletion layer, or that impurities are particularly concentrated in a single atomic layer or in a single layer or layers that are thinner than or equal to the depletion layer. It is designed to include one or more layers containing. In this embodiment below, the layer to which impurities are added is only one monoatomic layer, but it may be a polyatomic layer or may be composed of a plurality of these layers. A semiconductor device having stepped voltage-capacitance characteristics,
An example of a short channel high speed field effect transistor (FET) will be specifically explained. First, an example of stepped voltage-capacitance characteristics will be explained. A multilayer structure as shown in FIG. 1 is created by alternately growing Si molecular beam epitaxy layers and arsenic-doped layers on a substrate crystal using a Si molecular beam source and an arsenic molecular beam source. 11 is P
12 is a silicon semiconductor layer, 13 is a silicon layer in which impurities such as arsenic are localized, and 14 is an electrode. At this time, when adding arsenic, a shutter is placed in front of the Si molecular beam source to keep the amount of arsenic added to less than a monomolecular layer. FIG. 2 shows the distribution of impurity atoms in the multilayer structure thus created. Next, the characteristics when an electric field is applied to a semiconductor device having an impurity concentration distribution as shown in FIG. 2 will be described. The difference ΔE _i in electric field strength on both sides of the δ-function type impurity concentration distribution as shown in Figure 2 is:
It can be obtained by integrating the one-dimensional Poisson method d ² /dx ² =−1/ε _s ε ₀ ρ(x) (1). However, the potential energy, ρ(x)
is the charge distribution due to impurities, and ρ(x)=ρ ₀ δ(x−
a _i ). Here, ε _s is the specific electrostatic dielectric constant of the semiconductor, ε ₀ is the electrostatic dielectric constant of the vacuum, and a _i is the position of the impurity. By integrating equation (1) in the vicinity of a _i ,
The difference ΔE _i in electric field strength on both sides of a _i is ΔE _i =−[d/dx]a _i +0 a _i −0=1/ε _s ε ₀ ρ ₀ (2). Here, ρ ₀ is the impurity concentration per unit area
Substituting N _i [m ^-2 ], ΔE _i in equation (2) becomes ΔE _i =1.56×10 ^-9 N _i [V/m] (3). In this case, the capacitance C of a semiconductor layer with a thickness of d [m] is C per 1 m ² = ε _s ε ₀ S/d = 1.06×10 ^-10 1/d・[F/m ² ] (4) be. Therefore, the voltage-capacitance characteristic of the semiconductor device shown in FIG. 1 becomes step-like as shown in FIG. Further, as is clear from equation (3), the capacitance and voltage step sizes can be arbitrarily changed by appropriate impurity concentration and interval between impurity-doped layers. An example will be described in which an impurity region in which impurities are limited in a monoatomic layer or a thin layer similar thereto, which is a feature of the present invention, is applied to a field effect transistor. The impurities are localized and present in regions away from the channel. The carrier concentration is determined by the voltage applied to the gate electrode and the impurity distribution depending on the semiconductor layer containing impurities. Because of these structural features, it has the following advantages. (1) Since the channel region does not contain impurities, the carrier is not subject to impurity scattering. Therefore, higher mobility can be achieved. In the case of a normal MOSFET, the channel length (l) is designed to maintain a relationship of ∝Ni ^-2 with respect to the impurity concentration (Ni) of the substrate. However, in this case, no matter what manufacturing method is used, carrier mobility exceeding the level shown in Table 1 cannot be achieved depending on the impurity concentration of the substrate. On the other hand, in the semiconductor device of the present invention, as shown in Table 1, an FET with much higher mobility than the conventional example can be realized. In order to facilitate comparison, in the table, the added impurity concentration in the case of the present invention is shown as the effective impurity concentration averaged over the depletion region in the channel region. (2) Shorter channels, that is, miniaturization of semiconductor devices

[Table] Possible. Conventionally, it was thought that the limit of miniaturization of MOS transistors was determined by the impurity concentration in the Si substrate. In other words, in order to reduce the channel length l of a MOS transistor, it is necessary to increase the impurity concentration Ni of the substrate, and the minimum channel length l and impurity concentration Ni are determined by the relationship l∝Ni ^-2 as described above. be. but,
As the impurity concentration Ni increases, the spatial variation of the potential within the channel of the MOS transistor increases, so the upper limit of Ni is approximately 10 ²⁴
[m ^-3 ]. In this case, the average distance between impurity atoms is R ^* =
10 ^-8 m {100 Å}, therefore, the channel length of the MOS transistor is 10 times R ^* (10 ^-7 m
{1000 Å}) or less was impossible in principle. However, in the semiconductor device of the present invention, there are no impurities near the channel, and spatial fluctuations in the potential well can be made extremely small.
Therefore, it is possible to realize a short channel. For example, remove the same number of impurity atoms as the number of impurity atoms within a thickness of D from the interface between SiO ₂ and Si in a MOS transistor at a distance D from the interface between SiO ₂ and Si.
Let us consider the case where the addition is concentrated only in isolated monoatomic layers. The spatial variation of the channel potential of a MOS transistor when impurities are uniformly added to a conventional substrate is given by ~e ² /ε _s ε ₀ R ^* , whereas when impurities are added to a monoatomic layer, the potential changes The fluctuation becomes ~e ² /ε _s ε ₀ R ^* (R ^* /D) ³ . In other words, the variation in potential becomes smaller by (R'/D) ^three times. Here, R′ ^* is the average distance between impurity atoms in a monoatomic layer. If this is the upper limit of impurity concentration Ni = 10 ²⁴ m ^-3 , then R ^* = 10 ^-8 m, R' ^* = 0.5/10 ^-8 m, and D =
When it is 500 Å, the variation in the potential in the channel becomes 1/100 or less compared to the conventional case. Noise at high frequencies is also low because there is little variation in potential within the channel. (3) Variations in threshold values of a large number of semiconductor devices are reduced. Therefore, the yield is improved. This is because, as described above, there are no impurities in the vicinity of the channel, and spatial fluctuations in the potential wells are extremely small. When the spatial variation of the potential well is large, measuring how the drain current I _D rises depending on the gate voltage V _G yields the threshold voltage value (V _th ) of the gate voltage.
The tension stops. Moreover, the threshold voltage values of a large number of semiconductor devices will vary statistically. With the configuration of the present invention, these problems can be greatly reduced. That is, the rise of the current between the source and the drain becomes sharp near the threshold voltage. Example 1 Using a Si and arsenic molecular beam source, a Si single-crystal layer 12 with a thickness of a = 10 ^-7 m {1000 Å} was formed on an Si n-type substrate crystal 1, and As was deposited within the monoatomic layer to form a 10 ¹⁶ m thick layer of As. ^-2 {10 ¹² cm
^-2 } The doped Si layers 13 are grown alternately by the molecular beam epitaxial method to create the laminated structure shown in FIG. Furthermore, a shot key electrode 14 is formed by electron beam evaporation of Al on the surface of this laminated structure.
The area of the device is 10 ^-4 ×10 ^-4 m ² . The voltage-capacitance characteristic of this semiconductor device was step-like as shown in FIG. Thickness of Si molecular beam epitaxy layer: 10 ^-8 m {100 Å} to 10 ^-6 m {10000 Å}; concentration of impurity doped layer: 10 ¹⁵ m ^-2 {10 ¹¹ cm ^-2 } to 5×
Similar stepped voltage-capacitance characteristics could be obtained over a range of 10 ¹⁶ m ^-2 {5×10 ¹² cm ^-2 }. Embodiment 2 FIGS. 4 and 5 are cross-sectional views of a device showing each step of the manufacturing process of a semiconductor device according to the present invention. A silicon (Si) substrate 41 is mounted in a molecular beam epitaxial apparatus, and molecular beam sources of Si and boron (B) are prepared. Vacuum inside molecular beam epitaxial equipment
10 ^-9 Torr or less, 10 ^-6 m thick on Si substrate 41
A Si layer 42 is grown by molecular beam epitaxial growth, and then boron is deposited at a concentration of 5 in a monoatomic layer on the Si layer 42.
A Si layer 43 with a concentration of x10 ^-2 and a Si layer 44 having a thickness of 10 ^-7 m (1000 Å) are grown on this Si layer 43 by molecular beam epitaxial growth. FIG. 4 is a sectional view showing this state. In this example, the impurity is localized within a single atomic layer, but the impurity may be introduced into multiple layers. What is important in this case, unlike conventional impurity introduction methods, is to localize the impurity concentration so that it has substantially no statistical distribution. As the gate oxide film 56, the upper part of the multilayer structure shown in FIG.
This was used as a SiO ₂ film of Å. Also, the source and drain electrode regions 55 are formed by CVD method.
Arsenic was formed on the first semiconductor layer by thermal diffusion using the SiO ₂ film as a diffusion mask. The gate electrode 57 was formed by depositing metal Al on the gate oxide film 56. FIG. 5 is a sectional view showing this state. In this way, we were able to fabricate a FET (field effect transistor). Its channel length is 10 ^-7 m
(1000 Å), which would have been inoperable with FETs manufactured using conventional silicon process technology.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device having stepped voltage-capacitance characteristics, FIG. 2 is a diagram showing the impurity concentration distribution of the semiconductor device, and FIG. 3 is a diagram showing the voltage-capacitance characteristics of the semiconductor device. , 4 and 5 are cross-sectional views of an apparatus for explaining the manufacturing process of the semiconductor device of the present invention. 11, 41: semiconductor substrate, 13, 43: second semiconductor layer containing impurities, 12, 44: first semiconductor layer not containing impurities, 14, 57: electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor device having a semiconductor substrate, a first semiconductor layer provided on the substrate, and a second semiconductor layer provided close to the first semiconductor layer, The first semiconductor layer does not substantially contain impurities, and the second semiconductor layer contains impurities, and the second semiconductor layer is composed of a monoatomic layer, and the impurity concentration is substantially statistic. 1. A semiconductor device characterized by having no distribution. 2. The semiconductor device is a capacitor, and the first and second semiconductor layers are provided in a plurality of layers, and electrodes are provided above and below the first and second semiconductor layers. A semiconductor device according to scope 1. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a transistor, and the first semiconductor layer is provided with a channel. 4. A semiconductor device in which the channel is a potential well formed in the first semiconductor layer depending on the presence of the second semiconductor layer and an external electric field, wherein the first semiconductor layer A gate oxide film is formed on the surface of the first semiconductor layer, and a control electrode is further formed on the surface of the gate oxide film. A patent claim characterized in that the channel is formed at the interface on the control electrode side, and the second semiconductor layer contains an impurity that generates carriers of the opposite type to carriers moving in the channel. 3. The semiconductor device according to item 3. 5. The semiconductor device according to claim 1, wherein the second semiconductor layer contains Si.