JPH0444432A - Signal multiplex circuit and signal demultiplex circuit - Google Patents

Abstract

PURPOSE:To realize a channel of an optional band width as required by delaying 0th to (N-1)th filtered signals by delay of 0-(N-1) samples respectively, adding the results, converting the sum into a serial signal and outputting the serial signal as a signal subject to FDM multiplexing. CONSTITUTION:The circuit is provided with 1st-(N-l)th frequency conversion circuits 4-1-4-(N-1) and a k-th frequency conversion circuit 4-k applies frequency conversion of 0(Hz) fk=k.DELTAf(Hz). The center frequency of an input signal is frequency-converted from 0(Hz) to fk(Hz). Then the signal is given to filters 2-0-2-(N-1) tuned to a same frequency fk. Thus, a filter bank having a completely flat frequency characteristic in a band of each channel is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frequency division multiplexing (FDM) system, and in particular,
The present invention relates to a signal multiplexing/separating circuit that performs FDM multiplexing and demultiplexing of signals.

[Conventional technology]

In order to effectively multiplex/separate FDM signals, transformer multiplexers using digital signal processing are widely used.

Figures 3 and 4 show a conventional transformer multiplexer type multiplexing circuit (TMUX) and a separating circuit (TDUX), respectively.
) is shown.

In FIG. 3, the conventional transformer multiplexer type multiplex circuit includes an N fishway fast Fourier transform circuit (IFFT) 1,
0th to (N-1)th subfilters 2-0 to 2-(
N-1) and a parallel/serial conversion (P/S) circuit 3.

In FIG. 4, the conventional transformer multiplexer type separation circuit includes a serial/parallel conversion (S/P) circuit 5 and 0th to (
N-1) subfilters 6-0 to 6 (N-1) and an N-point fast Fourier transform circuit (FFT) 7.

The operation of the conventional transformer multiplexer will be explained below.

First, when inputting N input signals in a frequency range of fs, Δf = f s / N (
1) Consider FDM multiplexing at frequency intervals.

Here, f s −1/T
(2) is called the sampling frequency.

Conventional transformer multiplexers include, for example, M, G, Belanger and J, L, Daggett (M, G, Be
llanger and J, L, Daguet)
TDM-FDM) Lance Multiplexer: Digital Polyphase and FFT (TDM-FDMTra
nsmultjplexer:Digital Po1
yphase andF
199-1205. September 1974, (IEEE T
rans, vo 1. C0M-22, pp, 1199-
1205. Sep, 1974), the details will be omitted. Its characteristics are the individual signals X in FIGS. 3 and 4. (ZN), X, (ZN
), ..., Xk (ZN), ..., XN-1 (ZN) and ■. (ZN).

V (ZN), ..., Vk (ZN), =, VN
This means that -1(ZN) is a sample sequence of frequency Δf in equation (1).

[Problem to be solved by the invention]

Therefore, the signals X*(ZN), V*(Z
The frequency band N) can never exceed the frequency Δf.

That is, conventional TMUX as a filter bank.

As shown in Figure 5(A), the characteristics of TDUX are Δ
It will be limited to a frequency range f.

For example, FDM/TD, which is widely used in public line networks,
In the M l-lance multiplexer, Δf-4k
It is Hz. For this reason, in the telephone network, the bandwidth of the communication path is limited to 4 kHz, placing severe restrictions on the data transmission speed. Data transmission is the main communication medium of the future, and this constraint is too great.

The purpose of the present invention is to provide a signal multiplexing/demultiplexing system that performs FDM multiplexing/demultiplexing at intervals of Δf (Hz) as in the conventional method, except for the limitations of the conventional method described above, and can also provide a communication path of any bandwidth as required. The purpose is to provide circuits.

[Means to solve the problem]

The signal multiplexing circuit according to the invention has a sampling frequency fs
The 0th to (N-1)th input signals sampled at F
A signal multiplexing circuit that performs DM multiplexing and outputs FDM multiplexed signals, the 0th to (N-1)th input signals having center frequencies from 0Hz to 0.Δf to (N-1), respectively. ) and a demultiplexing means for demultiplexing into 0th to (N-1)th demultiplexed signals having 0th to (N-1)th frequencies represented by Δf; an N-fishway fast Fourier transform circuit that performs inverse fast Fourier transform of the demultiplexed signals of the 0th to (N-1)th signals to the 0th to (N-1)th inverse fast Fourier transformed signals; 1), respectively predetermined 0th to (N-th)
1) 0th to (N-1) filter circuits that perform the signal filtering and output the 0th to (N-1) filtered signals; a parallel/serial conversion circuit that adds O to (N-1) sample delays to the filtered signals of 1) and converts them into serial signals, and converts the serial signals into the FDM multiplexed signals. It is characterized by outputting as a signal.

The signal separation circuit according to the present invention is a signal separation circuit that separates FDM multiplexed signals of the 0th to (N1)th channels and outputs the 0th to (N-1) demultiplexed signals. and the 0th to (N-1th) of the FDM multiplexed signal
) a serial/parallel conversion circuit that applies a sample delay of 0 to (N-1) to each channel and performs serial/parallel conversion into 0-th to (N-1)-th parallel signals; The predetermined 0th to (N
-1) 0th to (N-1) filter circuits that perform signal filtering and output the 0th to (N-1)th filtered signals; 1) The filtered signal of an N-point fast Fourier transform circuit that performs fast Fourier transform on the fast Fourier transformed signal; and an N-point fast Fourier transform circuit that performs fast Fourier transform on the fast Fourier transformed signal; 1
), and the demultiplexing means demultiplexes the 0th to (N-1)th demultiplexed signals into the 0th to (N-1)th demultiplexed signals, respectively. It is characterized in that it is output as a digital signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, the signal multiplexing circuit according to an embodiment of the present invention includes first to (N-1)th branching circuits 4-1 to 4-4-.
It has the same configuration as that shown in FIG. 3 except that (N-1) is added. k-th (1≦to≦(N-1
)) branching circuit 4- has 0(Hz)-f, -k・Δf
(Hz).

Referring to FIG. 2, the signal separation circuit according to one embodiment of the present invention includes first to (N-1)th branching circuits 8-1 to 8-
It has the same configuration as that shown in FIG. 4 except that (N-1) is added. The second branching circuit 8- has a branching signal opposite to that of the second branching circuit 4-, that is, f*
(Hz) -0 (Hz).

conduct.

The operation of this embodiment will be explained below.

First, a signal multiplexing circuit (multiplexing circuit) will be explained with reference to FIG. Generally, the input signal is X, (Z)-Σ
It can be expressed as x, z-(3). Here, Z = e12zlT,, 6''2*f/Lm
(4). The purpose of the multiplexing circuit is (3)
Expression X, (Z) to f, - Δ f−k (fs /N)
(5) It is to transmit to a frequency position. To do this, first, we set the center frequency of the input signal in equation (3) to frequency 0
(Hz) to fi (Hz).

This means that in equation (4), z -4eIlg(C-1klT= e-1+2m/N
) k Z (5). The result is X, (Z;k) -Σ6-1+2g/N)k
ax , Z −(7).

Next, this signal can be passed through a filter tuned to the same <f. As such a filter, a basic low-pass filter G (Z) subjected to variable conversion according to equation (6) is used. Here, the basic low-pass filter G (Z) is expressed using sub-filters G and (ZN). That is, G (Z) -Σ g, Z-' 1Σ 2-phase G, (ZN) However, the subfilter G, (ZN) is L/N-1 G, (ZN) -Σ gspi++Z-"
(9) becomes. A bandpass filter G(Z;k) is obtained by subjecting G(Z) to demultiplexing according to equation (6).

Ru.

That is, G (Z;k)-Σ e I(2a/Nlk-Q ・Z-'G, (ZN) (10)
becomes. Therefore, the FDM output on the channel is G(Z;
k)X, (Z;k) vote Σ z −'G , (Z N ) e
l12y, 'Nlk・X, (Z;k) When this is multiplexed, the output is y (z) -Σ G(Z;k)Xk (Z;k)
-Σ Z-'G, (ZN) Σ 6 1 +
21 'Nl 龜・X, (Z;k) becomes. Here, Σ z-' is the P/S conversion, G, (ZN) is the subfilter, Σ eIL21+/N)"X, (z;k) is the IF
This can be achieved with FT. If this is achieved with hardware,
As shown in Figure 1.

For FDM demultiplexing, it is sufficient to perform the operation opposite to that described above, so the configuration is the same, but the direction of the signal can be reversed, resulting in the configuration shown in FIG. 2.

The signal multiplexing circuit of the present invention includes a conventional transmultiflexor TMUX as a special case. That is, in the conventional TMUX, the original signals X and (Z) only take values every N samples.

That is, in equation (7), the value is taken only when n = mN, and X, (Z;k)-ΣX SIN Z -'''9-X,
(ZN) (13), which is the same as the conventional TMUX shown in FIG.

As a useful case for the present invention, consider the case where the input signal has a value every N7/2 samples. In this case, n − m
When N/2 is set, equation (7) becomes X h (Z;
k)-X (-1)"X, pty2Z IN""-
Xk (Z””;k) (14). Therefore, the demultiplexing operation simply does nothing for the even channels of the input signal, and for the odd channels, only inverts the polarity of the input signal for odd samples.

An example of the present invention is the above-mentioned double sampling (N/
(with a value every second sample) is particularly useful. That is, since the sampling frequency is 2Δf, the input signal X, (Z) of the multiplexing circuit or the output signal V, (Z) of the branching circuit
) can extend beyond Δf to 2Δf. The situation is shown in FIG. 5(B).

The signal multiplexing/separating circuit according to the invention makes it possible to realize a filter bank with completely flat frequency characteristics within the band of each channel.

FIG. 6 shows an example of a further application of the invention.

This provides complete line connections for each channel between M FDM systems. In Figure 6, 10-1~
10-M is a transmitting/receiving device between each system, 11-1~
11-M is a signal branching circuit according to the present invention, 12-1 to 12
-M is a signal multiplexing circuit according to the present invention. 13 is a baseband exchange.

FIG. 7 shows the characteristics of the switching network shown in FIG.

FIG. 7(A) shows the frequency characteristics of the signal branching circuits 11-1 to 11-M, and FIG. 7(B) shows the frequency characteristics of the signal multiplexing circuits 12-1 to 12-M. Since the signal passes through one of the branching circuits and the multiplexing circuit, the overall frequency characteristic is as shown in FIG. 7(C). That is, it is designed so that the overall frequency characteristic becomes completely flat when combined with adjacent channels.

Therefore, in order to pass a signal with a wider band than Δf, it is sufficient to simply use a plurality of adjacent channels.

〔Effect of the invention〕

The present invention provides the following effects.

(1) A filter bank with completely flat frequency characteristics within each channel can be realized by a sampling method that is doubled at most. Therefore, free application within the band is possible.

(2) By designing a switching network in which the overall frequency characteristics of the cascade-connected branching circuit and multiplexing circuit become flat when adjacent channels are added, a switching network that can pass signals of any bandwidth without distortion can be created. realizable.

(3) The above-mentioned switching network makes it possible to realize a public communication network that can transmit not only voice but also data at various transmission speeds using a simple modulation method.
It becomes easy to realize a DN system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a signal multiplexing (combining) circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a signal separation (branching) circuit according to an embodiment of the present invention, and FIG. A block diagram showing a signal multiplexing (combining) circuit using a conventional transformer multiplexer. Figure 4 is a block diagram showing a signal separating (branching) circuit using a conventional transformer multiplexer.
Fig. 5 is a diagram showing the frequency characteristics of the conventional signal multiplexing/separating filter bank of the present invention, (A) shows the frequency characteristic of the conventional filter bank, (B) shows the frequency characteristic of the present invention, and Fig. 6 shows the frequency characteristic of the conventional signal multiplexing/separating filter bank. Did F
FIG. 7 is a block diagram showing a DM exchange, and FIG. 7 is a diagram showing the communication channel frequency characteristics of the switching network of FIG. Frequency characteristics of the circuit, (C) shows the overall frequency characteristics of (A) and CB). 1.N fishway fast Fourier transform circuit (IFFT), 2-0
~2- (N-1)... Sub filter, 3... Average/
Serial conversion circuit, 4-1 to 4- (N-1)... Branching circuit, 5... Series/parallel conversion circuit, 6-0 to 6 (N-1)...
・Subfilter, 7...N-point fast Fourier transform circuit (
FFT), 8-1 to 8- (N-1)... Branching circuit, 1o-1 to 10-M... Transmitting/receiving device, 11-1 to 1
1-M...branching circuit, 12-1 to 12-M...multiplexing circuit, 13...baseband exchanger. Machine. Figure 1: Multiplexer circuit (TMUX) Figure 2: Branch circuit (TDUX) Figure 3: S circuit (TMUX) Figure 4: 8 circuit (TDLIX) Figure 7 (B)

Claims (1)

[Scope of Claims] 1. In a signal multiplexing circuit that FDM-multiplexes 0th to (N-1)th input signals sampled at a sampling frequency fs and outputs an FDM-multiplexed signal, comprising: The 0th to (N-1)th input signals are input to the 0th to (N-1)th frequencies whose center frequencies are 0Hz and 0. a frequency conversion means for converting the frequency into the 0th to (N-1)th frequency-converted signals; and a frequency conversion means for converting the frequency to the 0th to (N-1)th frequency-converted signals; an N-point inverse fast Fourier transform circuit that performs inverse fast Fourier transform on the fast Fourier transformed signal; and predetermined 0th to No. (N-
1) 0th to (N-1) filter circuits that perform signal filtering and output 0th to (N-1) filtered signals; a parallel/serial conversion circuit that adds 0 to (N-1) sample delays to the filtered signals of 1) and converts them into serial signals, and converts the serial signals into the FDM multiplexed signals. A signal multiplexing circuit characterized by outputting signals. 2. The frequency conversion means includes means for outputting the 0th input signal as it is as a 0th frequency-converted signal, and means for outputting the 0th input signal as a 0th frequency-converted signal; 2. The signal multiplexing circuit according to claim 1, further comprising first to (N-1) frequency conversion circuits that perform frequency conversion to (N-1) frequency-converted signals. 3. In the signal separation circuit that separates the FDM multiplexed signals of the 0th to (N-1)th channels and outputs the 0th to (N-1)th demultiplexed signals, The 0th to (N-1)th of the FDM multiplexed signal
) a serial/parallel conversion circuit that applies a sample delay of 0 to (N-1) to each channel and performs serial/parallel conversion into 0-th to (N-1)-th parallel signals; The predetermined 0th to (N
-1) 0th to (N-1) filter circuits that perform signal filtering and output 0th to (N-1) filtered signals; 1) The filtered signal of an N-point fast Fourier transform circuit that performs fast Fourier transform on the fast Fourier transformed signal; and an N-point fast Fourier transform circuit that performs fast Fourier transform on the fast Fourier transformed signal; 1
), and outputs the signals as the 0th to (N-1)th demultiplexed signals, respectively.