JPH044454A - System for protecting register access - Google Patents

Abstract

PURPOSE:To improve the general usefulness, functional expandability, and reliability of this system by discriminating the propriety of access to a register on the basis of a comparison result between the system controlling link of a processor requesting the access and the system controlling link of a common device having the register. CONSTITUTION:An address discriminating section 39 discriminates whether or not a received register oriented address is to a special register on the basis of the discrimination bit of the address. When the discrimination bit is '1' and the access is to the special register, the section 39 feeds a discrimination requesting signal to an SRL discriminating section 35. Then the section 35 compares the system controlling link SRL received from a processor 1 with the system controlling link SRL of a common device 3 itself stored in an SRL storing section 37 and discriminate the propriety of the access from the processor 1 to the special register. Therefore, when processor 1 makes access to a register in the common device 3 at a special address area, the access can be realized by making comparison between the system controlling links only and the general usefulness, functional expandability, and reliability of this system are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a multiprocessor system having a plurality of processors and one or more common devices having registers accessed by the plurality of processors. Concerning register access protection methods.

(Prior Art) In a multiprocessor system, registers provided in a common device such as a common memory device or a common data channel device are accessed by a plurality of processors. However, if all processors are allowed to access special registers related to system configuration control, such as registers that control the connection relationship between data channel devices and processors, and registers that accept reset requests for common devices from processors, , which may impede the stability of the entire system. That is, if one processor runs out of control due to a failure, for example, and accesses a special register of a common device by mistake, the operation of the common device may be inhibited, and the normal operation of the entire system may not be guaranteed.

In order to avoid the above-mentioned phenomenon, conventionally, the master/
There is a method of determining whether or not to execute this instruction according to the processor mode by setting a processor mode that represents the hierarchy between processors such as slave, and using an instruction that exclusively executes access to a special register. It is used. More specifically, when the processor mode is mask, execution of an instruction dedicated to accessing a special register is allowed, but when the processor is in slave mode, execution of this instruction is not allowed. . If there is only one processor in the mask mode in the system, the special registers in the common device can be protected from failures of the slave processors that occupy the majority of the system.

(Problem to be Solved by the Invention) In a processor using a general-purpose microcomputer, it is difficult to add a dedicated instruction that only accesses a special register, and the above-mentioned protection measures cannot be implemented. There is.

In addition, in order to realize complicated special register access permission conditions, it is necessary to provide multiple types of processor modes and dedicated instructions, which causes problems in terms of functional expandability and general versatility in terms of logic specifications.

Specifically, as shown in FIG. 2, three types of processor modes are provided: mask, submaster, and slave, and common device A,
There are two types: dedicated instruction 1 for accessing the special register of H and allowing access only in master mode, and dedicated instruction 2 for accessing the control register of common device C and allowing access only in master mode or submask mode. It is necessary to provide the following, and the functionality expandability and versatility as a logical specification are poor.

The present invention has been made in view of the above, and its purpose is to provide a highly reliable register access protection system with a simple configuration without adding any dedicated instructions.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the register access protection method of the present invention provides a register access protection system that includes a plurality of processors and one or more common registers having registers accessed by the plurality of processors. A register access protection method for a multi-processor system having a device, in which a system control link is set for each processor that expresses system control authority in levels, and a system control link that expresses the conditions for receiving access from each processor in levels. is provided in each common device, and when a processor accesses a register in the common device located in a specific address area, the system control link of the accessing processor is compared with the system control link of the common device that has the register, and the system control link of the common device having the register is compared. The gist is to determine whether access is possible based on the comparison results.

(Operation) In the register access protection method of the present invention, when a processor accesses a register in a common device located in a specific address area, the system control link of the accessing processor and the system control link of the common device that has the register are connected. and determine whether or not access is possible based on the comparison result.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of a register access protection system according to an embodiment of the present invention. In this embodiment, a special register 31 provided from the processor 1 to the common device 3
In order to access the processor 1, a system control link SRL that expresses the system control authority in terms of levels is set in the processor 1, and a system control link SRL that expresses the reception conditions for access from the processor 1 in terms of levels is set in the common device 3. set and processor 1's system control link SRL
and the system control link SRL of the common device 3,
Based on the comparison result, it is determined whether the processor 1 can access the special register 31 of the common device 3.

This system control link SRL is composed of 2 bits, for example, as shown in Table 1 below, and access from the processor 1 to the common device 3 is set as shown in Table 1.

Table 1 In Table 1, "O" allows access from processor 1 to common device 3, and "x" denies access from processor 1 to common device 3. It is shown that.

In addition, the processor 1 uses the special register 31 of the common device 3.
When accessing the special register 31 of the common device 3,
The register specification address sent from the processor 1 to the common device 3 is as shown in Table 2 below. ~15
(16th bit), a determination bit (16th bit 1) indicating whether the register is a special register, and an internal device register specification field (17th bit to 31st bit) specifying a register in the common device. It consists of 32 bits (15 bits).

When the determination bit is "0", it indicates a register other than a special register, and when the determination bit is "1", it indicates a special register. In this way, it is possible to clearly determine whether or not the access is to a special register using the determination bit.

Table 2 In FIG. 1, between processor 1 and common device 3,
System control link SR from processor 1 to common device 3
an SRL transmission line 5 for transmitting L; and an address line 7 for transmitting an address from the processor 1 to the common device 3;
A data line 9 for data transmission between the processor 1 and the common device 3 and a line (not shown) for sending a control signal for accessing the register of the common device 3 from the processor 1 are connected.

The common device 3 receives the address transmitted from the processor 1 via the SRL storage section 37 storing its own system control link SRL and the address line 7,
The address determination unit 39 determines whether or not the access is to a special register, and the system control link SRL of the processor 1 transmitted from the processor 1 via the SRL transmission line 5 and the common information stored in the SRL storage unit 37 an SRL determination unit 35 that compares the system control link SRL of the device 3 itself and determines whether access to the special register of the processor 1 is possible; and a register access control unit 33;
It consists of a special register 31. Note that the address determination unit 39 supplies a determination request to the SRL determination unit 35 based on the address determination result.

In the configuration as described above, when a register access instruction is executed in the processor 1, the system control link SRL of the processor 1 and the special register 31 of the common device 3 to be accessed are specified as shown in Table 2. The register specified address is from processor 1 to SR.
L transmission line 5 and address line 7 respectively to the common device 3 and also to the processor 1.
In the case of writing data from to the special register 31 of the common device 3, the write data is sent from the processor 1 via the data line 9 to the common device 3.

The register designated address sent to the common device 3 is received by the address determination unit 39 of the common device 3. The address determination unit 39 determines whether or not the received address is an access to a special register based on the determination bit of the received register specified address. Then, if the determination bit is 1 and the access is to a special register, the address determination section 39 supplies a determination request signal to the SRL determination section 35, so that the SRL determination section 35
The system control link SRL received from the common device 3 is compared with the system control link SRL of the common device 3 itself stored in the SRL storage unit 37 to determine whether access to the special register from the processor 1 is possible. As a result of this determination, if access to the special register is permitted, the SRL determination section 35 sends the request to the register access control section 3.
Accordingly, the register access control unit 33 executes writing to or reading from the special register 31 from the processor 1 .

Further, if the register designation address received from the processor 1 by the address determination unit 39 is not for special register access, that is, if the determination bit is 0, the register is immediately accessed without determining the system control link SRL. Allow access.

In the above embodiment, a case has been described in which the SRL of the common device 3 is stored in the SRL storage unit 37, but the method is not limited to this, and the method of setting the system control link SRL of the common device 3 is as follows. In addition to the method of always providing a fixed system control link SRL in the common device 3 as in this embodiment, there is a method of providing a system control link SRL bit in the special register 31. System control link SRL for device 3
Once the value of S RL is set, only processors with SRL values equal to or smaller than this S RL value can be accessed. For example, if the SRL value of the common device 3 is "00", only the processor with the SRL value of "00" can update the SRL value of the common device 3, and this will cause unnecessary SRL It is possible to prevent the value from being updated.

In the above embodiment, the case where there is one processor 1 and one common device 3 has been described, but the present invention is not limited to this. is also applicable in the same way. In this case, the S between the processor and the common device is
RL transmission line 5, address line 7, data line 9, etc. will be bus-connected between multiple processors and common devices.

[Effects of the Invention] As described above, according to the present invention, when a processor accesses a register in a common device located in a specific address area, the system control link of the accessing processor and the common device having the register are The system control link is compared with the system control link, and access permission is determined based on the comparison result, so it can be achieved relatively easily by just comparing the system control link without adding special instructions like in the past. It is possible to improve versatility, expandability, and reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a register access protection system according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram that implements access conditions for a conventional special register. DESCRIPTION OF SYMBOLS 1... Processor 3... Common device 31... Special register 35... SRL judgment section, 37... SRL storage section, 39... Address judgment section. Agent Patent Attorney Hidekazu Miyoshi-14=

Claims (1)

[Claims] A register access protection method in a multiprocessor system having a plurality of processors and one or more common devices having registers accessed by the plurality of processors, the system control link expressing system control authority to each processor at a level. A system control link is provided in each common device that expresses the conditions for receiving access from each processor in terms of levels, and when a processor accesses a register in the common device in a specific address area, the A register access protection method characterized by comparing a system control link with a system control link of a common device having the register, and determining whether access is possible based on the comparison result.