JPH044455A - Memory access arbitration circuit - Google Patents

Abstract

PURPOSE:To easily prepare firmware in the case a request signal is received from one processor, by sending no permission signal when another request signal is received from another processor and stopping a permission signal being sent when a reset signal is received from the another processor. CONSTITUTION:A permitting means 4 prevents an access conflict to a between processors 2 and 3 and is initialized by a reset signal to stop the sending of a permission signal. The processors 2 and 3 are initialized by the reset signal and stop the sending of request signals. When the request signal is sent to the permitting means 4 and one of the processors 2 and 3 receives the permission signal, the processor which receives the permission signal can gain the access to the memory 1, since the sending of the permission signal to the processors 2 and 3 is stopped due to the initialization. Therefore, when firmware is prepared for instructing the operations of the processors 2 and 3, the firmware can be prepared easily, because it is not necessary to consider about flag erasure.

Description

[Detailed Description of the Invention] [Summary] When multiple processors share one memory and send and receive commands and data via the memory, it is easy to create firmware that instructs the operations of the multiple processors. For the purpose of facilitating the creation of firmware regarding a memory access arbitration circuit, the following method is used to send out a request signal requesting permission to access one memory and the memory, and to grant access in response to the request signal. In an apparatus including a plurality of processors, which continues sending the request signal and accesses the memory when a permission signal is received, and stops the request signal being sent by a reset signal, when a request is made from one processor. When a signal is received, if no request signal is received from other processors, a permission signal is sent, and when a request signal is received from one processor, a request signal is received from another processor. In this case, the configuration is such that a means is provided for stopping the sending of the permission signal when the reset signal is received without sending the permission signal.

(Industrial Application Field) The present invention allows multiple processors to share one memory,
The present invention relates to a memory access arbitration circuit that facilitates the creation of firmware that instructs the operations of the plurality of processors when commands and data are exchanged via the memory. In an information processing system, when multiple devices or circuits within one device operate under control by exchanging commands and data between respective processors, multiple processors alternately access one memory, In some processors, commands and data are exchanged between processors by having the other processor read commands and data stored in the memory by one processor.

For example, if one processor becomes the main processor and controls the interface with the higher-level device, and the other processor becomes the slave processor and controls the internal circuits of the device, the main processor receives instructions from the higher-level device. In order to execute the work specified by the command, the slave processor writes commands and data to the slave processor in memory, the slave processor reads the written commands and data from this memory, executes the work specified by the command, and sends the execution results to the host processor. When the main processor writes the status to be notified to the memory, the main processor reads this status and reports it to the host device.

In this way, when multiple processors share a single memory, it is necessary to prevent conflicting accesses to the memory by each processor, but this makes it difficult to create firmware that instructs the operations of the processors. It is necessary not to become

[Conventional technology]

Conventionally, when multiple processors share one memory, it is determined whether or not the memory can be accessed depending on whether a flag is set at the starting address of the memory. Therefore, when one processor accesses memory, it first checks whether a flag is set at the first address of the memory. If the flag is not set, it determines that the memory can be accessed, and After setting the flag at the address, access the required memory area. and,
When the access to the memory is completed, the flag set at the first address of the memory is canceled.

Therefore, if a flag is set at the start address of memory, it will be determined that the memory is being used by another processor, wait until the setting of this flag is canceled, and when the flag is canceled, the start address of this memory will be After setting a flag at an address, the required memory area is accessed.

The operations of such a processor are directed by the firmware.

[Problem to be solved by the invention]

As mentioned above, in the past, the processor processor set a flag at the first address of memory according to firmware instructions.
The flag that was set is being canceled.

If the flag is not canceled, other processors will not be able to access the memory, so the processor that set the flag must cancel the setting of the flag when it completes using the memory.

Incidentally, although the operator may forcefully reset the device, this reset does not change the contents of the memory. However, since the processor is initialized by reset, if the processor is reset while accessing memory, the flag set at the first address of memory will remain as is unless the processor clears it. It happens.

In this case, multiple initialized processors have flags still set at the first memory address, so
This is a serious problem in that the memory cannot be accessed and the device remains stopped, so when a reset is instructed, the processor clears the flags set in the memory and then returns to the initialization state. Need to migrate.

For this reason, special care must be taken when creating firmware that instructs processor operations.
There is a problem in that a large number of man-hours are required during firmware development and design, making it uneconomical.

In view of these problems, it is an object of the present invention to provide a memory access arbitration circuit that can facilitate the creation of firmware by adding a small amount of hardware.

[Means to solve the problem]

FIG. 1 is a block diagram illustrating the invention in detail.

Processors 2 and 3 send control signals to memory 1 to access memory 1, and exchange commands and data with each other via memory 1.

That is, for example, when the processor 2 accesses the memory 1 and writes a command or data to the processor 3, it sends a request signal requesting permission to access the memory 1 to the permission means 4.

If the permission means 4 has not received a request signal from the processor 3, it sends a permission signal to permit access in response to the request signal from the processor 2, but if it has already received a request signal from the processor 3, A permission signal is not sent in response to a request signal from the processor 2.

When the processor 2 receives the permission signal from the permission means 4,
While continuing to send the request signal, a control signal is sent to the memory 1, commands and data are sent to the memory 1 via the bus 5, and written into the memory 1.

When the processor 2 finishes writing commands and data, it stops sending the request signal, so the permission means 4 stops sending the permission signal to the processor 2.

The processor 3 sends a request signal to the permission means 4 in order to read commands and data written in the memory 1, but the permission means 4 does not give permission to the processor 3 while the request signal from the processor 2 continues. No signal is sent.

Therefore, the processor 3 continues to send the request signal and waits for the permission signal to be received. When the request signal from the processor 2 stops, the permission means 4 accepts the request signal sent by the processor 3 and sends a permission signal to the processor 3.

After receiving the permission signal, the processor 3 sends a control signal to the memory 1, reads out the commands and data written by the processor 2 in the memory 1 via the bus 5, and based on these commands and data, the processor 2 issues instructions. carry out work.

When the reset signal enters the processor 2.3 and the permission means 4, the processors 2 and 3 stop the Noriquest signal being sent, and the permission means 4 stops the permission signal being sent. Then, the processor 2 initialized by the reset signal sends a request signal to the permission means 4 again, and upon receiving the permission signal, writes the command and data into the memory 1.

[Effect]

With the above configuration, the permission means 4 prevents access conflict between the processors 2 and 3 to the memory 1, and is initialized by a reset signal to stop sending permission signals.

Further, processors 2 and 3 are initialized by a reset signal and stop sending request signals.

Therefore, since the initialized processors 2 and 3 have stopped sending the permission signal, they send the request signal to the permission means 4 again, and the processor 2 or 3 that has received the permission signal sends the request signal to the permission means 4 again.
can access memory 1.

Therefore, when creating firmware that instructs the operations of the processors 2 and 3, there is no need to take flag erasure into consideration, and the firmware can be created easily.

[Embodiment] FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation of FIG. 2.

When processor 2 accesses memory 1, Figure 3 ■
As shown in FIG. Logic “0°” is converted into NOR circuit 8
Send to.

The flip-flop 11 initially outputs logic “0” to AN.
Since it is sent to D circuits 12 and 13, AND circuit 13
is sending a logic “0” to the NOR circuit 8. Therefore,
When the NOT circuit 6 sends out a logic “0”, the NOR circuit 8
sends a logic "1" to the OR circuit 10 and the AND circuit 12, and the OR circuit 10 sends a logic "1" to the flip-flop 11.

As shown in FIG. 3 CLK, a clock is input to the flip-flop 11 from the terminal CLK, and when the OR circuit 10 sends out a logic "1", it is set by the fall of the clock, and the logic "1" is sent to the AND circuit. 12 and 13.

At this time, since the NOR circuit 8 is sending a logic "1" to the AND circuit 12, the AND circuit 12 sends a logic "1" as a permission signal to permit access to the memory 1, as shown in FIG. Send to processor 2.

Upon receiving the logic "1" as the permission signal, the processor 2 sends a control signal to the memory 1 to
Commands and data are sent to and written into the memory 1 via the memory 1.

The processor 3 is delayed from the processor 2 and sends a logic "1" as a request signal to the NOT circuit 7 as shown in FIG. Therefore, the NOT circuit 7 sends the logic "0" to the NOR circuit 9, but since the logic "1" is input from the AND circuit 12 to the NOR circuit 9, the NOR circuit 9 sends the logic "0" to the OR circuit. 10 and the AND circuit 13, and the AND circuit 13 outputs the logic “0” to the NOR.
It remains sent to the circuit 8 and processor 3.

When the processor 2 completes the access to the memory 1 and sends the logic "0" indicating the stop of the request signal to the NOT circuit 6 (as shown in FIG. 3), the NOR circuit 8 also outputs the logic "0" to the OR circuit 10 and the AND circuit 12.

Therefore, as shown in FIG. 3, a logic "0" is sent to the processor 2, indicating that the permission signal sent from the AND circuit 12 has stopped. Further, since the OR circuit 10 sends a logic "0" to the flip-flop 11, the flip-flop 11 is reset at the falling edge of the clock and sends a logic "0" to the AND circuits 12 and 13.

At this time, the processor 3 continues to send the logic "1" as the request signal, as shown in FIG.
The OT circuit 7 continues to send out logic "0". Therefore, when the AND circuit 12 sends a logic "0" to the NOR circuit 9 as shown in FIG.

Therefore, the flip-flop 11 is set at the falling edge of the clock and sends a logic "1" to the AND circuits 12 and 13. Therefore, as shown in FIG. 3, the AND circuit 13 sends a logic "1" to the processor 3 as a permission signal. Read commands and data stored in l.

When the processor 3 completes the access to the memory 1 and sends a logic "0" indicating the stop of the request signal to the NOT circuit 7 as shown in FIG. and is sent to the AND circuit 13.

Therefore, as shown in FIG. 3, a logic "0" is sent to the processor 3, indicating that the permission signal sent from the AND circuit 13 has stopped. Also, since the OR circuit 10 sends a logic "0" to the flip-flop 11, the flip-flop 11 is reset at the falling edge of the clock.
A logic "0" is sent to AND circuits 12 and 13.

The processor 2 again operates the N01 circuit 6 as shown in FIG.
Logic "1" is sent to the processor 2 from the AND circuit 12 as described above, as shown in FIG.
When a reset signal is input to the processors 2 and 3 and the flip-flop 11, the processor 2 stops sending out the request signal at the falling edge of the reset signal, and becomes a logic "0" as shown in FIG. ” is sent to the N01 circuit 6.

Also, since the flip-flop 11 is reset and sends a logic "0" to the AND circuits 12 and 13, the processor 2
The logic "1" as the permission signal that was being sent out stops, and the logic "0" is sent out as shown in FIG.

In this embodiment, a circuit using a request signal and a permission signal has been described, but the write enable (WE) signal and word selection (RAS) signal used when the processor drives the memory
You can also use signals.

〔Effect of the invention〕

As explained above, the present invention makes it possible to prevent contention when multiple processors access a single memory by simply adding a simple circuit. There's no need. Therefore, when creating firmware that instructs the operation of the processor, there is no need to consider erasing the flag, and the firmware can be created easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a time chart explaining the operation of FIG. 2. In the figure, 1 is a memory, 2 and 3 are processors, '4 is a permission means, 5 is a bus, '6 and 7 are N07 circuits, 8 and 9 are NOR circuits, 10 is an OR circuit, 11 is a flip-flop, 12, 13
is an AND circuit.

Claims (1)

[Claims] When one memory (1) and a request signal requesting permission to access the memory (1) are sent, and a permission signal granting access to the request signal is received, Continuing to send the request signal, the memory (1
) and which stops the request signal being sent by a reset signal (2) and (3), when receiving a request signal from one processor, the If no request signal is received, a permission signal is sent, and when a request signal is received from one processor, if a request signal is received from another processor, no permission signal is sent, and the A memory access arbitration circuit comprising means (4) for stopping a permission signal being sent when a reset signal is received.