JPH044464A - Accumulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

The present invention relates to a fixed-point arithmetic digital arithmetic circuit, and more particularly to an accumulator that calculates the sum of a data string and further performs a rounding operation to an effective bit length. [0002]

[Conventional technology]

In an arithmetic unit that performs digital arithmetic, the data string DI
(n): An operation (accumulation) that calculates the sum of (n=1 to N) occurs frequently. Especially in digital signal processing,
Accumulation is frequently used in convolution operations, matrix operations, etc. At this time, in fixed-point arithmetic accumulators, in order to minimize calculation errors, the bit width of the adder and register is designed to be larger than the bit width of the input data so that overflow does not occur. In order to accurately represent the result DO with a finite bit width, for example, with the same bit width as the input data string, a rounding operation (rounding to the nearest whole number, here one O) is performed. Note that the rounding operation involves adding 2 to the cumulative result, shifting the addition result to the right using a shifter, and adding 2 to the accumulated result.
This is an operation in which the lower bits of digits or more are rounded down. Once the number of accumulations and the bit width of the final output are determined, the number of digits m of rounding operations is
is also determined. [0003] FIG. 5 is a block diagram showing an example of the configuration of a conventional accumulator, in which 1 is an adder for accumulation, 2 is a register, 3 is a reset circuit, 4 is an adder for rounding operations, and 5 is an adder for accumulation. This is a shifter that performs a right shift. Here, adders 1, 4 . The bit widths of register 2 and shifter 5 are designed to be larger than the bit width of input DI, as described above. [0004] The operation of the accumulator in FIG. 5 will be described below with reference to the operation timing diagram in FIG. 6. The adder 1 in FIG. 5 has an input data string D shown in FIG. 6(b).
I (n): (n = 1 to N) and the output Q (n); (n = 1 to N) of register 2 shown in Figure 6 (C) are synchronized with the clock shown in Figure 6 (a). The signals are sequentially input to one and the other input terminals, respectively. The added result A (n); (n=1 to N) is input to the register 2 and sequentially fetched at the next clock. That is, Q
(n)=A (n-1). [0005] Through the above series of operations, the input data string DI (n)
are accumulated. However, under the control of the reset circuit 3, the register 2 is set in advance to II O11, that is, Q (0)
must be reset to =0. Through the above calculation, the sum of the input data string DI (n) can be obtained as the output Q (N) of register 2, but in order to express it with a finite bit length with high accuracy as described above, rounding operation (rounding off) is necessary. It is. That is, it is necessary to perform an operation of adding 2 and discarding the lower bits below the 2 digit. In order to perform such rounding operations, an adder 4 for rounding operations is provided, which is separate from the adder 1 for accumulation.
(n), that is, the output Q (N), and addition data R (R=2) for rounding operation are added. The result of this operation (see FIG. 6(d)) is shifted to the right by the shifter 5, and the lower bits below the 2 digit are rounded off and output (see FIG. 6(e)). [0006]

[Problem to be solved by the invention]

As described above, when performing a rounding operation in a conventional accumulator, after calculating the sum of the input data string DI (n) for the rounding operation, the adder 4 for the rounding operation is used to further Must be processed. That is, there is a problem that the circuit scale and calculation time become large. In particular, in digital signal processing, etc., real-time processing is important, and in the frequent accumulation, shortening the calculation time is an important issue, and reducing the circuit scale is also an important issue. [0007]

[Means to solve the problem]

The accumulator of the present invention mainly includes an adder and a register having a bit width larger than the bit width of an input data string.
By inputting the input data string to one input terminal of the adder, inputting the output of the register to the other input terminal of the adder, and inputting the output of the adder to the register, the input data string is accumulated and a rounding operation is performed. A fixed-point arithmetic accumulator that performs rounding operations to an arbitrary bit width and outputs the result by adding up the addition data for the data, shifting the resulting operation result to the right using a shifter, and truncating the lower bits. According to claim 1, an initial value setting circuit is provided for initializing the contents of the register to addition data for rounding operation. [0008] Further, in claim 2, a multiplexer is provided at the other input terminal of the adder, and the addition for rounding operation is performed only when the first data of the input data string is input to one input terminal of the adder. Select the data and input it to the other input terminal of the adder, and when the second and subsequent data in the input data string are input to one input terminal of the adder, select the output of the register and input it to the other input terminal of the adder. The multiplexer is controlled to input to the other input terminal. [0009]

[Effect]

According to the configuration of claim 1, the addition data for rounding operations is set in advance in the initial value setting circuit, and the addition data for rounding operations is set in the register before performing the accumulation. The input data string is accumulated using the addition data of as the initial value. [0010] Furthermore, according to the configuration of claim 2, when the first data of the input data string is input, the addition data for rounding operation is input to the adder at the same time, which is similar to the configuration of claim 1. To,
The input data string is accumulated to add data for rounding operations. As a result, it is possible to accumulate the input data string and add the addition data for the rounding operation without the need for an adder for the rounding operation, and the calculation time is the time required for only accumulation without rounding. is equal to As a result, the circuit scale and calculation time can be significantly reduced. [0011]

【Example】

FIG. 1 is a block diagram showing an embodiment of an accumulator according to the invention. In FIG. 1, 1 is an adder, 2 is a register, and 5 is a shifter, which are the same components as in the conventional example shown in FIG. Here, adder 1. Register 2 and shifter 5 are designed to be larger than the bit width of input data DI. Reference numeral 6 denotes an initial value setting circuit for setting addition data for rounding operations in the register 5. [0012] The operation of the accumulator in FIG. 1 will be described below with reference to the operation timing diagram in FIG. 2. The adder 1 in FIG. 1 has an input data string D shown in FIG. 2(b).
I (n); (n = 1 to N) and the output Q (n): (n = 1 to N) of register 2 shown in Figure 2 (C) are synchronized with the clock shown in Figure 2 (a). The signals are sequentially input to one and the other input terminals, respectively. Added result A
(n); (n=1 to N) is input to the register 2 and sequentially fetched at the next clock. That is, Q
(n)=A (n-1). [0013] Through the above series of operations, the input data string DI (n)
are accumulated. However, under the control of the initial value setting circuit 6, the register 2 is set in advance as addition data R (R
=2) is set. That is, Q (0)=R. Setting the initial value can be easily accomplished in the same manner as the process of resetting register 2 in a conventional accumulator. [0014] Through the above calculation, the sum of the input data string DI (n) is obtained as the output Q (N), but at this time, the input data R (R = 2) for the rounding operation has already been calculated. The data string DI (n) has been accumulated, and the operation result Do is then shifted to the right using the shifter 5, and the lower bits below the 2 are rounded off to be output (see Figure 2 (d)).
You can perform rounding operations simply by doing this. [0015] According to this embodiment, the addition data R (R=2) for rounding operation is not required as in the conventional example, but an adder for rounding operation is not required.
can be added to the accumulated result, and the circuit scale can be reduced by eliminating the need for an adder for rounding operations. Also,
Unlike the conventional example, an addition operation is not performed, and the addition data R is simply initialized in the register 2, so that the calculation time required for accumulation and rounding operations can be reduced. [0016] Next, FIG. 3 is a block diagram showing an embodiment of the accumulator of the invention of claim 2. In FIG. 3, 1 is an adder, 2 is a register, and 5 is a shifter, which are the same components as in the conventional example shown in FIG. Again, adder 1. Register 2 and shifter 5 are designed to be larger than the bit width of input data DI. A multiplexer 7 selects the output of the register 2 or the initial value (R) which becomes the addition data for the rounding operation and applies it to the other input terminal of the adder 1. [0017] The operation of the accumulator in FIG. 3 will be explained with reference to the operation timing diagram in FIG. 4. The adder 1 in FIG. 3 has an input data string DI shown in FIG. 4(b).
(n): (n=1 to N) and the output Q of the multiplexer 7 shown in FIG. 4(C) (n): (n=1 to N) are synchronized with the clock shown in FIG. and the other input terminal respectively. The added result A (n); (n=1 to N) is input to the register 2 and sequentially fetched at the next clock. [0018] Here, the multiplexer 7 inputs the input data string DI (n
) only when the first data DI (1) is input, the addition data R for the rounding operation is selected and inputted to the other input terminal of the adder 1, (2) to DI (N)), the multiplexer 7 is controlled so that the output from the register 2 is selected and input (feedback) to the other input terminal of the adder 1. That is, Q (0)=R. [0019] By the above calculation, Q (N) has input data string DI
(n) is calculated, but at this time the input data string DI (n) has already been accumulated with respect to the addition data R (R=2) for the rounding operation, and the rest is to calculate the operation result DO.
The rounding operation can be realized by simply shifting the value to the right using the shifter 5 and outputting it (see FIG. 4(d)). Similarly to the invention of claim 1, this embodiment also does not require a second adder for rounding operations, and furthermore, the operation time is equal to the time for only accumulation without rounding operations, which reduces the circuit size and operation time. It is possible to reduce the [0020]

【Effect of the invention】

According to the accumulator of the invention of claim 1, by providing an initial value setting circuit and setting addition data for rounding operation in the register before accumulating the input data string, and by setting the addition data for rounding operation in the register, According to the accumulator, a multiplexer is provided at the other input terminal to the adder, and the addition data for rounding operation is sent to the other input terminal of the adder only when the first data of the input data string is input. When the second and subsequent data in the input data string is input to one input terminal of the adder, the output from the register is selected and input to the other input terminal of the adder. Instead of accumulation, the input data string is accumulated using addition data for rounding operations, so there is no need for addition time for rounding operations, which is equal to the time for only accumulation without rounding operations, and especially If used in digital signal processing where real-time performance is important, the effect of speeding up is extremely large. [0021] Furthermore, since the second adder for rounding operations is no longer required and the adder, which has the largest circuit scale among the components of the accumulator, can be eliminated, the circuit scale of the accumulator can be reduced by approximately half. It has an excellent effect of reducing the amount of water used. Furthermore, the accumulator of the present invention can be used as a component of a program-controlled arithmetic unit (processor), and the setting of addition data to a register, that is, the operation of an initial value setting circuit, can be performed using the resources of the processor under program control. Although the method of doing this can also be easily realized, in this case as well, it is possible to realize an intrusive processor that can obtain the effects of the above invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an accumulator according to an embodiment of the invention according to claim 1.

[Figure 2] FIG. 2 is an operational timing diagram of the accumulator of FIG. 1.

FIG. 3 is a block diagram showing the configuration of an accumulator according to an embodiment of the invention according to claim 2.

[Figure 4] FIG. 4 is an operational timing diagram of the accumulator of FIG. 3.

[Figure 5] FIG. 5 is a block diagram showing the configuration of a conventional accumulator.

[Figure 6] FIG. 6 is an operation timing diagram of the accumulator of FIG. 5.

[Explanation of symbols]

1 Adder 2 Register 5 Shifter 6 Initial value setting circuit 7 Multiplexer

[Document core]

[Figure 11 drawing [Figure 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

Claims (2)

[Claims] 1. The main components include an adder and a register having a bit width larger than the bit width of an input data string, the input data string is input to one input terminal of the adder, and the output of the register is sent to the adder. By inputting the output of the adder to the other input terminal of the register, the input data string is accumulated, addition data for rounding operation is added, and the result of the operation is transferred to the shifter. The accumulator is a fixed-point arithmetic accumulator that performs a rounding operation to an arbitrary bit width by right-shifting and discarding the lower bits, and outputs the resulting result. An accumulator characterized by being provided with an initial value setting circuit for initializing data. 2. The main components include an adder and a register having a bit width larger than the bit width of the input data string, the input data string is input to one input terminal of the adder, and the output of the register is sent to the adder. By inputting the output of the adder to the other input terminal of the register, the input data string is accumulated, addition data for rounding operation is added, and the result of the operation is transferred to the shifter. A fixed-point arithmetic accumulator that performs a rounding operation to an arbitrary bit width by right-shifting and discarding the lower bits, and outputs the result, and a multiplexer is provided at the other input terminal of the adder. , the first of the input data string
Only when the th data is input to one input terminal of the adder, the addition data for the rounding operation is selected and input to the other input terminal of the adder, and the second and subsequent data of the input data string is selected. The multiplexer is controlled such that when the data is input to one input terminal of the adder, the output of the register is selected and input to the other input terminal of the adder. Calculator.