JPH0444706U - - Google Patents

Info

Publication number
JPH0444706U
JPH0444706U JP1990086875U JP8687590U JPH0444706U JP H0444706 U JPH0444706 U JP H0444706U JP 1990086875 U JP1990086875 U JP 1990086875U JP 8687590 U JP8687590 U JP 8687590U JP H0444706 U JPH0444706 U JP H0444706U
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor device
bonding
hybrid
bottom plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990086875U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990086875U priority Critical patent/JPH0444706U/ja
Publication of JPH0444706U publication Critical patent/JPH0444706U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す断面図、第
２図はこの考案の要部の構造を説明するための分
解斜視図、第３図はこの考案の変形実施例を示す
断面図、第４図は従来の技術を説明するための断
面図、第５図はその分解斜視図、第６図は従来技
術の不都合を説明するための断面図である。 １……底板、２……回路基板、３，４……回路
パターン導体、５，８……接着剤、６……デバイ
スホール、７……半導体デバイス、９……ボンデ
ングワイヤ、１２……導電箔。 Fig. 1 is a sectional view showing an embodiment of this invention, Fig. 2 is an exploded perspective view for explaining the structure of the main part of this invention, and Fig. 3 is a sectional view showing a modified embodiment of this invention. FIG. 4 is a sectional view for explaining the conventional technique, FIG. 5 is an exploded perspective view thereof, and FIG. 6 is a sectional view for explaining the disadvantages of the conventional technique. DESCRIPTION OF SYMBOLS 1... Bottom plate, 2... Circuit board, 3, 4... Circuit pattern conductor, 5, 8... Adhesive, 6... Device hole, 7... Semiconductor device, 9... Bonding wire, 12... conductive foil.

Claims (1)

【実用新案登録請求の範囲】 底板に回路基板が積層され、回路基板に形成さ
れたデバイスホールに半導体デバイスを収納し、
半導体デバイスの電極と回路基板に形成された回
路パターンとの間をボンデングワイヤによつて電
気的に接続したハイブリツトＩＣにおいて、 上記回路基板に形成したデバイスホールの底面
を導電箔によつて塞ぎ、この状態で回路基板を底
板に接着し、デバイスホールの底面に露出した上
記導電箔に半導体デバイスを接着して構成したハ
イブリツトＩＣ実装構造。[Claims for Utility Model Registration] A circuit board is laminated on a bottom plate, a semiconductor device is housed in a device hole formed in the circuit board,
In a hybrid IC in which an electrode of a semiconductor device and a circuit pattern formed on a circuit board are electrically connected by a bonding wire, the bottom surface of a device hole formed in the circuit board is closed with a conductive foil, A hybrid IC mounting structure is constructed by bonding the circuit board to the bottom plate in this state and bonding the semiconductor device to the conductive foil exposed at the bottom of the device hole.
JP1990086875U 1990-08-20 1990-08-20 Pending JPH0444706U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990086875U JPH0444706U (en) 1990-08-20 1990-08-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990086875U JPH0444706U (en) 1990-08-20 1990-08-20

Publications (1)

Publication Number Publication Date
JPH0444706U true JPH0444706U (en) 1992-04-16

Family

ID=31818781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990086875U Pending JPH0444706U (en) 1990-08-20 1990-08-20

Country Status (1)

Country Link
JP (1) JPH0444706U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07305587A (en) * 1994-05-13 1995-11-21 Sun Tec:Kk Consolidation type auger screw for drilled earth

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07305587A (en) * 1994-05-13 1995-11-21 Sun Tec:Kk Consolidation type auger screw for drilled earth

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