JPH0444749U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional circuit. In the figure, 1 is an enable signal, 2 is a data signal, 3 is a clock signal, 4 is an input interface circuit, 5 is EN, 6 is DATA, 7 is CLK,
8 is an error detection circuit, 9 is a DET signal, 10 is an OR
gate, 11 is a FIFO memory, 12 is a read clock generation circuit, 13 is a read clock signal, 1
4a is DATA3, 14a is DATA4, 15 is select data, 16 is a reset signal, 17 is a priority encoder circuit, 18 is a select signal, and 19 is a selector circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A plurality of interface circuits that input enable signals, data, and clocks input from a plurality of external devices, an error detection circuit that is connected to each of the plurality of interface circuits and detects data errors, and the plurality of error detection circuits described above. a priority encoder that encodes the output of the output signal;
a FIFO memory that stores the input data; a selector that selects the outputs of the plurality of input interface circuits and the output of the FIFO memory that stores the input data; and a selector that is controlled by an output signal of the priority encoder; and a read clock generation circuit that reads data from the FIFO memory using the output signal of the input signal selection circuit.