JPH044484A - Microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the need of an external circuit which monitors error information by providing a comparator circuit which compares data of an error information generation circuit with those at an error information input terminal in addition to a system data bus. CONSTITUTION:Data of eight bits are read out from a memory 2 of a 9-bit constitution and, at the same time, a parity bit of the 9th bit is directly inputted to the error information input terminal 4 of a microcomputer 1. The microcomputer 1 outputs the parity of the read-out 8-bit data from an error information generation circuit 5 and compares the parity with that of the data at the input terminal 4 at a comparator circuit. Therefore, the need of an external circuit to improve the system reliability has been eliminated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microcomputer.

[Conventional technology]

In systems using conventional microcomputers,
To improve system reliability, system data
It has been common practice to add error information to data on the bus and monitor the error information.

For example, there is a method of using a 9-bit memory and setting the 9th bit as a parity bit.

[Problem to be solved by the invention]

The above-described conventional microcomputer has the disadvantage that it does not have a terminal for inputting error information, and therefore requires an external circuit to monitor error information.

[Means to solve the problem]

The microcomputer of the present invention has system, data,
In addition to the bus, there is also an error information generation circuit that generates error information on the data on the bus, an error information input terminal that inputs error information on the data on the bus from the outside, and an error information generation circuit and error information input terminal. and a comparison circuit for comparing data.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, this embodiment includes an 8-bit system data bus 3 and an error information input terminal 4 for inputting a parity bit.

At the same time as reading 8-bit data from the 9-bit memory 2, the 9th parity bit is directly input to the error information input terminal 4 of the microcomputer 1. At this time, the microcomputer 1 outputs the parity of the 8-bit read data from the error information generation circuit 5, and compares it with the data at the error information input terminal 4 in the comparison circuit 6.

If the comparison results are different, abnormality processing is performed.

Therefore, in the present invention, no external circuit is required to improve the reliability of the system.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage that when applied to a microcomputer, no external circuit is required to improve the reliability of the microcomputer system.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention. 1...Microcomputer, 2...
Memory, 3...System data bus, 4.
... Error information input terminal, 5 ... Error information generation circuit, 6 ... Comparison circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] An n-bit system data bus, an error information generation circuit that generates error information of the data on the bus, an error information input terminal that inputs error information of the data on the bus from the outside, an error information generation circuit, and an error information generation circuit. A microcomputer characterized by comprising a comparison circuit that compares data with an information input terminal.