JPH0444873B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention restores divided signals of multiple channels obtained by dividing a signal on a single transmission path back to the original signal on a single transmission path. The present invention relates to a divided signal restoration device.

[Background technology and its problems]

When performing signal transmission or signal processing on a wideband signal on a single transmission path, the signal frequency (or data clock frequency) is reduced by dividing the single wideband signal into multiple channels and expanding the time axis for each channel. Then, signal transmission and signal processing are performed for each of these multiple channel divided signals,
It is known that the signals of each channel are then time-base compressed and restored to the original wideband signal on a single transmission path.

For example, in recent years, the development of high-resolution (high-definition or high-definition) video systems with as many as 1125 scanning lines has progressed, and it has become necessary to transmit such high-resolution video signals and perform digital signal processing. . The frequency band of this high-resolution video signal is wide, for example, about 25M to 30MHz, and the sampling clock frequency when digitizing it reaches, for example, about 70M to 80MHz, so it is necessary to process the signal using standard TTL. is almost impossible. Here, ECL (Emitsuta Katsupurudo)
Also called logic or CML. ), but such high-speed elements such as ECL are generally expensive, and have the drawback that they consume a lot of power, generate a large amount of heat, and are difficult to dissipate. In addition, ROM is used during signal processing.
(read-only memory) and RAM (random access memory) are often used, and since these memories are often slow and TTL interface type, it is difficult to interface with high-speed elements such as ECL. be.

For this reason, the input video signal is divided into N on the time axis (N is an integer of 2 or more), the clock signal frequency is reduced to 1/N as N-channel signals, and signal processing is performed for each of these channels. After
Restoration to the original high frequency clock video signal is being carried out. In this case, at the stage of restoring the signal, in the past, the time axis was restored for each channel independently, and then a switch circuit was used to switch to the original data order and connect the data between each channel. We are conducting
Not only does the circuit configuration become complicated due to the complexity of controlling the timing of time axis restoration between each channel and the switching timing of the switch circuit, but also data loss occurs because the data of each channel is connected by switching the switch. The disadvantages that adverse effects such as continuity and noise contamination are likely to occur cannot be avoided.

[Purpose of the invention]

In view of the above-mentioned circumstances, the present invention has been devised to write data into memory without using switching means such as a switch when compressing the time axis of the signals of each divided channel and restoring them to the original single signal. The purpose of the present invention is to provide a divided signal restoring device which realizes functions of time axis compression and switching of signals of each channel by controlling readout, and has a simple circuit configuration and is free from adverse effects caused by switching.

[Summary of the invention]

That is, the feature of the divided signal restoration device according to the present invention is that a broadband signal on a single transmission path, such as a high-resolution video signal, is divided into N parts (N is an integer of 2 or more) for each fixed unit time, and each time axis is In a divided signal restoration device that compresses the time axis of the N-channel divided signals obtained by expansion and restores them to signals on a single transmission path, the N-channel divided signals are stored.
A memory circuit such as a RAM (Random Access Memory), a write address control circuit that controls the divided signals of the N channels to be written into the memory circuit while sequentially circulating through the channels, and the N channels written in the memory circuit. and a read address control circuit for controlling the divided signals to be read out in accordance with the order of the signals on the original single transmission path.

〔Example〕

First, prior to explaining a specific example of the present invention, the basic operation for obtaining an N-channel signal that is an input signal to the apparatus of the present invention will be explained with reference to the drawings.

Figure 1 shows a screen S displayed by a high-resolution (high-definition or high-definition) video signal, which is an example of a wideband signal on a single transmission path.On this screen S, each horizontal line is multiple pieces,
For example, it is divided into four equal parts to form so-called vertically divided screen blocks A, B, C, and D. As an input signal to the device of the present invention, for example, four channels of video signals corresponding to each of the screen blocks A, B, C, and D are divided from the original single video signal that displays the entire screen S. I am assuming that it was taken out. For example, as shown in Figure 2, the video signal VS on the original single transmission path
Divide 1H period (1 horizontal period) into 4 equal parts A, B, C,
D, these can be expanded on the time axis and distributed to four channels ChA, ChB, ChC, and ChD, respectively. In the video signal VS in Fig. 2,
For example, regarding the signal for 1H from time t ₁ to time t ₅ , the signal for H/4 corresponding to the above block A from time t ₁ to t ₂ is divided into the 1H range from time t ₁ to t ₅ . Expand the time axis (expand by 4 times) and channel
The signal from t ₂ to t ₃ is time-extended from t ₂ to t ₆ and distributed to channel ChB, and the signal from t 2 to t ₃ is distributed to channel ChB.
Stretch the time axis of the signal at ~t ₄ to t ₃ ~ t ₇ and channel it
The signal from t ₄ to _{t 5} is time-axis extended to t ₄ to _{t 8} and distributed to channel ChD.

Here, it is assumed that there are, for example, 1856 pieces of sampling data during 1H of the original video signal VS, and these data are sequentially zeroed in the order of time.
Each data D ₀ is numbered from 1855 to 1855.
~D ₁₈₅₅ , the correspondence relationship between these data and the data distributed to each channel ChA to ChD is as shown in FIG. 3, for example. This third
In the figure, when the sampling clock period of the original video signal VS is T _SP , 1H (1 horizontal period)
is equal to 1856T _SP , and the clock period _TCK of each channel ChA to ChD is 4T _SP . Also, the original signal
1856 pieces of data D ₀ for 1H period, which is the unit time of VS
~D ₁₈₅₅ is divided into four equal parts along the time axis, and each divided data of 464 pieces is distributed to each channel.
ChA to ChD are divided into 1 hour periods each. Specifically, data D ₀ to _{D 463} are assigned to channel ChA, and data D ₄₆₄ to _{D 927} are assigned to channel ChA.
to ChB, data D ₉₂₈ to _{D 1391} to channel ChC,
Furthermore, data D _{1392 to D 1855} are allocated to channels ChD, and at this time, as explained in conjunction with _FIG .
The data D ₀ to D ₄₆₃ ) in the figure is expanded four times on the time axis, and the signal VS is expanded between t ₁ and _{t 5} of channel ChA.
Data between t ₂ and _{t 3} (D ₄₆₄ to D ₉₂₇ in Figure 3), t ₃ to
Data between t ₄ (D ₉₂₈ to D ₁₃₉₁ in Figure 3), and t ₄ to _{t 5}
The data in between (D ₁₃₉₂ to D ₁₈₅₅ in Figure 3) are each expanded by a factor of 4, and the data from t ₂ to D 1 of channel ChB are expanded by 4 times.
t ₆ , channel ChC between t ₃ and _{t 7} , and channel ChD between t ₄ and _{t 8} , respectively. Therefore, as shown in FIG. 3, for example, 4 immediately after time t ₁
Among the data of each channel ChA to ChD obtained during the sampling period of 4T _SP (=T _CK ), the data of three channels ChB, ChC, and ChD are obtained at time t ₁
The data within the previous 1H period are D ^-H ₈₁₂ , D ^-H ₁₁₆₀ , and D ^-H ₁₅₀₈ . Here, the symbol indicating the data in Figure 3 is
- attached to the right shoulder of D _o (n=0,1,...,1855)
H or +H indicates data existing in the 1H period before or after the 1H period between times t ₁ to t ₅ out of each data of the original signal VS. That is, on the display screen, pixels displayed by data D ^-H _o , D _o , D ^+H _o, etc. having the same number n are at the same horizontal position, and the data
With respect to the pixel of D _o , the pixel of data D ^{- H} _o is located one line above, and the pixel of data D ^{+ H} _o is located one line below.

Each data signal divided into, for example, four channels is transmitted or signal-processed for each channel, and then supplied to the divided signal restoring device of the present invention.

FIG. 4 is a block circuit diagram showing an embodiment of the divided signal restoring device of the present invention. In FIG. 4, divided signals of the channels ChA, ChB, ChC, and ChD are supplied to four input terminals 1A, 1B, 1C, and 1D. These input terminals 1A~
Each input divided signal from 1D is sent to a memory circuit 2 consisting of a RAM (random access memory) or the like. Writing and reading data to and from the memory circuit 2 is performed by a write address control circuit 3 and a read address control circuit 4, and a restoration operation as shown in FIG. 5, for example, which is the reverse of the operation shown in FIG. 2, is performed. ing.

In this figure 5, the time of channel ChA
The data for 1H from t ₁₁ to t ₁₅ is time-axis compressed to 1/4, and the restored output video signal VSO is output from time t ₁₄ to t ₁₅ .
Similarly, below, the channel ChB
The output signal VSO is compressed by 1/4 time axis between t ₁₂ and t ₁₆ .
From t ₁₅ to _{t 16} , the period from t ₁₃ to t ₁₇ of channel ChC is compressed to 1/4 to t 16 to t ₁₇ of VSO, and also from t ₁₆ to t 17 of channel ChD.
The period between t ₁₄ and _{t 18} is compressed to 1/4 and placed between t ₁₇ and _{t 18} of the VSO, respectively. In this case, the synchronization timing (time
t ₁₁ , t ₁₅ , t ₁₉ , ...), the output video signal VSO
Timing of H synchronization signal (time t ₁₄ , t ₁₈ ,...)
are shifted by 3/4H, so match these timings (or make the phase difference by H time)
In order to do this, for example, a restoring operation as shown in FIG. 6 may be performed.

That is, in this FIG. 6, the time axis of the signal for 1H (for example, between time t ₂₁ and time t ₂₆ ) of the first channel ChA is compressed to 1/4, and this time axis compressed H/4 minute signal is compressed to 1/4. The signal is the restored output video signal
It is arranged at the first H/4 portion (for example, from time _t25 to _t26 ) of the next 1H of VSO (for example, from time _t25 to _t29 ). Next, between 1H of channel ChB (e.g. t ₂₂ ~
t ₂₇ ) is also compressed on the time axis by 1/4, and the output signal
During _the H/4 period (for example _, t ₂₆
~t ₂₇ ). Similarly, channel ChC
Signal and channel between 1H (t ₂₃ to t ₂₇ ) of
The signal between 1H of ChD (between t ₂₄ and t ₂₈ ) is also 1/
H/4 interval (between t _{27 and t 28) that follows the part corresponding to channel ChB in the output signal VSO (between t 26 and t 27 ) ,} and the H/4 interval that follows this. (between t ₂₈ and t ₂₉ ).

The operation for restoring the video signal divided into four channels ChA to ChD into a single video signal VSO, particularly the write and read operations of the memory circuit 2, will be described below.

A write clock signal and a read clock signal from a clock signal generation circuit 5 are supplied to a write address control circuit 3 and a read address control circuit 4, respectively, for controlling writing and reading of data to and from the memory circuit 2, respectively. There is. These clock signals are synchronized with the data clock (period _TCK ) of each channel supplied via the clock input terminal 6, for example, and each control signal 3 _is , 4 alternately perform a write operation and a read operation on the memory circuit 2.
It is set to repeat once. FIG. 7 shows an example of data write and read operations during one data clock period _TCK .

That is, in FIG. 7, one clock period
Divide _TCK into 8 equal parts, and divide these 8 sections into 4 read sections R1 to R4 and 4 write sections W.
1 to W4 alternately, R1, W1, R2, W2,
They are arranged in the order of R3, W3, R4, and W4.
In each read section R1 to R4,
According to the data order of the original video signal, D _o ,
D _o+1 , D _o+2 , D _o+3 are read in the order, and in each write section W1 to W4, each channel is
ChA, ChB, ChC, ChD data D・A,D・
B, D・C, D・D are written cyclically.

That is, FIG. 8 shows each channel ChA~
This is a timing chart showing the relationship between the data of ChD and the data of the restoring force signal VSO. For example, during one clock period _TCK immediately after time _t25 , the sampling data is D ₀ , D ₁ , D ₂ , D ₃ are read out from the memory circuit 2 to form the signal VSO, and each _channel ChA, ChB,
Data appearing in ChC, ChD D ^+H ₀・A,
D ₈₁₂ ·B, D ₁₁₆₀ ·C, and D ₁₅₀₈ ·D are written into the memory circuit 2 in each write section W1, W2, W3, and W4, respectively.

By the way, when the memory capacity (number of words) of the memory circuit 2 in FIG. 4 is set to 1856 words, which is equal to the number of data for 1H of the original video signal, and these data are stored in the word of the address equal to that number, In other words, data D ₀ ~ _{D 1855} is assigned to address 0 ~
When storing each in 1855 words, data D ₀ to _{D 463} belonging to channel ChA are at address 0.
~463 memory block contains data belonging to channel ChB D ₄₆₄ ~ _{D 927} stores address 464 to 927 memory block data belonging to channel ChC
D ₉₂₈ to _{D 1391} are stored in memory blocks at addresses 928 to 1391, and data belonging to channel ChD.
_D1392 to _D1855 are stored in memory blocks at addresses 1392 to 1855, respectively. In this case, if the data numbers are the same, the data existing in the other H period of the original video signal, for example the above-mentioned
D ^-H ₀ , D ₀ , D ^+H _{0 ,} etc. are all written to the word at the same address, for example the word at address 0, so new data is not written before the previously written data is read. It is necessary to perform address control. Such inconvenience may occur immediately after time t ₂₅ , t ₂₆ , t ₂₇ , t ₂₈ in FIG. 6, but for example, immediately after time t ₂₅ ,
As shown in the figure, in interval W1 after data D ₀ at address 0 is read out in interval R1, data D ^{+ H} ₀ is written to the word at the same address 0 in memory circuit 2, so data corruption etc. Inconveniences have been avoided. This also applies to other times, such as immediately after t ₂₆ , t ₂₇ , and t ₂₈ .

Therefore, the write address control circuit 3
In each write period W1, W2, W3, W4 within the data clock period _TCK of the divided channel,
Data D _K1・A, of each channel ChA, ChB, ChC, ChD appearing during this _clock period TCK,
Control may be performed such that D _K2 ·B, D _K3 ·C, and D _K4 ·D are written cyclically to addresses equal to the respective data numbers. Further, the read address control circuit 4 may read data at addresses that are sequentially increased by 1 in each read period R1, R2, R3, and R4 within the data clock period _TCK . The data read out from the memory circuit 2 follows the data order of the original video signal and is taken out via the output terminal 7.

Next, FIG. 9 shows another embodiment of the present invention, in which each channel is supplied to each input terminal 1A to 1D.
The sampled data of ChA to ChD are converted into parallel data by serial/parallel converters 11A to 11D, respectively, and then supplied to the memory circuit 12. In this case, in order to simplify the explanation, only one bit of the sampling data will be considered, and the serial/parallel converters 11A to 1
In 1D, it is assumed that serial data of 1 bit each of 8 sampling data is converted to 8-bit parallel data. Here, when the number of data for 1H of the original video signal is 1856 as described above, the number of parallel data after the above conversion is 232, and for each channel, each
This is parallel data of 58 pieces. Therefore,
58 pieces of parallel data corresponding to channel ChA are stored at addresses 0 to 57 of the memory circuit 12, and similarly, 58 pieces of parallel data corresponding to channels ChB, ChC, and ChD are stored at address 58 of the memory circuit 12. ~115, 116~173, and
174 to 231, respectively.

In order to control writing and reading of such a memory circuit 12, a write address control circuit 1 is provided.
3. The read address control circuit 14 and the clock signal generation circuit 15 operate in substantially the same manner as the circuits 3, 4 and 5 shown in FIG. Since the low frequency is reduced to 1/8, as shown in Figure 10, the 8T _CK period is one cycle, and the time is
_TCK read section R1 to R4 and write section W
1 to W4 are arranged alternately to control reading and writing to the memory circuit 12. Then, each read section R1, R2, R
3 and R4, the data D _o ~D _o+7 , D _o+8 ~ _{D o+15} , D _o+16 ~
D _o+23 and D _o+24 to D _o+31 are read, and in each write section W1, W2, W3, and W4, the parallel data D _k1 A to D o of each channel are read.
D _k1+7・A, D _k2・B〜D _k2+7・B, D _k3・C〜
D _k3+7・C, D _k4・D to D _k4+7・D are written cyclically. Furthermore, the 8-bit parallel data sequentially read out from the memory circuit 2 in each read interval, that is, in 2T _CK cycles, is converted into 8-bit serial data in the parallel/serial converter 17, and 8 bits per 2T _CK are converted into 8-bit serial data. Serial data, that is, high-speed data whose data clock period is equal to the frequency of the original video signal of _TSP , is outputted via the output terminal 7.

According to the embodiment of the present invention described above, the number of data for one line of the original video signal (for example, 1856 pieces)
By using one memory circuit 2, 12, so-called line memory, having a memory capacity of 1,856 words (for example, 1856 words), by controlling the write address and read address for this memory circuit 2, 12, the time axis of the divided signal of each channel can be adjusted. Compressing and connecting the compressed signals of each channel on the time axis can be performed, and the divided signal can be easily restored with a circuit size approximately 1/2 smaller than that of a restoration device that uses a conventional changeover switch. Ru. In addition, the writing and reading clocks to the memory circuit only need to be at the original sampling clock frequency even when dividing signal data is written directly, and serial/parallel conversion is performed on the input side, and parallel/serial conversion is performed on the output side. By performing each of the above, writing and reading control using a low frequency of the divided signal, such as the data clock, becomes sufficient.

Note that the present invention is not limited to the above-mentioned embodiments. For example, the number of divided channels of a signal on a single transmission path is not limited to 4, but is generally divided into N channels (N is an integer of 2 or more). The signal can be restored to the original signal on a single transmission path. Furthermore, the signal on the original single transmission path is not limited to a video signal, and the unit time is not limited to 1H (one horizontal period).

〔Effect of the invention〕

According to the divided signal restoring device according to the present invention, time-base compression and compressed signals are performed when restoring N-channel divided signals obtained by dividing a signal on a single transmission path into N into the original single signal. Since the switching connection is performed by writing and reading control for one memory circuit, the divided signal can be easily restored using a simple circuit configuration with a small circuit scale.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a screen displayed by a video signal, which is an example of a signal on a single transmission path before division, and FIGS. 2 and 3 illustrate an example of the division operation of the single video signal. FIG. 4 is a block circuit diagram showing one embodiment of the present invention; FIGS. 5 and 6 are timing charts for explaining different examples of the restoration operation of the divided signal; 7 is a diagram showing the read and write timings of the memory circuit in FIG. 4, FIG. 8 is a timing chart for explaining the data correspondence during the divided signal restoration operation in FIG. 6, and FIG. FIG. 10, a block circuit diagram showing another embodiment of the present invention, is a diagram showing read and write timings of the memory circuit in FIG. 9. 1A, 1B, 1C, 1D...divided signal input terminals,
2, 12... Memory circuit, 3, 13... Write address control circuit, 4, 14... Read address control circuit, 5, 15... Clock signal generation circuit, 7... Single signal output terminal, 11A, 11B, 11C, 11
D... Serial/parallel converter, 17... Parallel/serial converter.

Claims (1)

[Claims] 1 The divided signals of N channels obtained by dividing the signal on a single transmission path into N parts (N is an integer of 2 or more) for each fixed unit time and expanding the time axis of each are compressed in the time axis and re-simplified again. A divided signal restoration device for restoring signals on one transmission path includes a storage circuit that stores the N-channel divided signals, and a write control that controls writing of the N-channel divided signals in the storage circuit while sequentially circulating the channels. A division characterized in that it has an address control circuit, and a read address control circuit that controls the N-channel divided signals written in the storage circuit to be read out in accordance with the order of the signals on the original single transmission path. Signal restoration device.