JPH0444967B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a data transmission device that primarily transmits data between systems that operate asynchronously. [Prior Art] Conventionally, the common method for transmitting data between asynchronous systems was to use FIFO (first-in, first-out) memory as a buffer between systems.
(Refer to August 1984 issue, pages 268 to 270), FIFO memory simply has a data buffering function, so if such FIFO memory is used for data transmission between asynchronous systems, multiple asynchronous The problem is that systems can only be connected in series, and the overall system connected by FIFO memory is just a pipeline processing mechanism using simple cascade connections, which has an extremely low degree of freedom. It was hot. In response to this, the applicant has developed and filed an application for a data transmission device that can provide greater flexibility when constructing overall data by connecting asynchronous systems (Japanese Patent Application No. 60-33035). , Tokugansho
60-33036). This data transmission device will be explained below. FIG. 2 is a diagram showing the system of the data transmission device, in which 5 is a data transmission path, 2a
~2c is the branching part, 3a~3c is the confluence part, 1a~1
c is a processing element, and 4 is an interface. In such a device, packet data flowing from an external system via the interface 4 reaches any one of the processing elements 1a to 1c while circulating between the network elements 3a and 2a to 2c, and is sent to each processing element 1a. After the distributed processing is performed in ~1c, the processing results are collected by the network elements 3b and 3c, and sent again to the external system via the interface 4. Further, FIGS. 3 and 4 show an example of an asynchronous self-running shift register used in the data transmission path 5. In FIG. In Figure 3, 6 is a parallel data latch, 7 is a parallel data latch, and 7 is a parallel data latch.
is composed of a 3-input NAND8 and a 2-input NAND9, 10, and provides a rising edge trigger to the parallel data latch 6 (hereinafter referred to as C element).
It is. An asynchronous self-running shift register is a register that automatically shifts input data in the output direction without using a shift clock, provided that the next register is empty, and it is a register that automatically shifts input data in the output direction without using a shift clock. It has a function.
This asynchronous self-running shift register is composed of a parallel data latch 6 and a C element 7. The C element 7 receives two inputs, P0 and P3, and outputs two outputs, P1 and P2. The internal state of 7 is determined by the states of these four signals P0 to P3,
As shown in the table below, there are nine states, _S0 to _S8 . In the following description, it is assumed that logical values 0 and 1 correspond to low level and high level signal values, respectively.

[Problem that the invention seeks to solve]

By the way, the above-mentioned data transmission device can be used to configure an arithmetic processing device, and in this arithmetic processing device, there are cases in which it is generally desired to observe various states of various functional parts, and the method for doing so is to use data transmission. One possibility is to observe the data flowing along the road. However, in the data transmission device described above, the data transmission path is constructed using a self-propelled shift register, and data is propagated very quickly, usually 25 to 50 nsec, so it is difficult to observe various functional parts from the data. It is something that cannot be done. The present invention has been made in view of such problems, and an object of the present invention is to provide a data transmission device that can slowly transmit data and propagate it little by little when necessary. [Means for Solving the Problems] The present invention provides a data transmission device in which a data transmission path is configured using an asynchronous free-running shift register consisting of a data latch and a C element. and a transfer timing control means for controlling the output timing of the control signal of at least one C element in response to the instruction. [Operation] In this invention, when the transfer timing control means is activated, the transfer timing control means stops outputting the control signal of the C element, and when an instruction is given from the instruction means, the transfer timing control means stops outputting the control signal from the C element. It outputs a signal. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a data transmission device according to an embodiment of the present invention. In the figure, 30 is a transfer timing control means, which includes a D-type flip-flop 31, a negative logic AND gate 32, a negative logic OR gate 33, a C
It is composed of an element 34, inverters 35a to 35e, a toggle switch 36, resistors 37a and 37b, and a capacitor 38. 39 is a momentary switch for instructing the data transfer timing. In this embodiment, the C elements 7 are constructed in two stages, and the C elements 7i and 34 are constructed using open collector type four-input NAND gates. Next, the operation will be explained. When the toggle switch 36 is ON, the transmission line operates normally. and toggle switch 36
When turned OFF, the output of inverter 35a becomes 0.
Therefore, the data propagated through the transmission path is C
It reaches element 7h and is temporarily stopped there. At this time, the momentary switch 39 is normally off, but when it is pressed, the clock input of the D-type flip-flop 31 becomes 1, and the Q output of the D-type flip-flop 31 becomes 1. As a result, the P2 output of the C element 34 becomes 1, and the P1 output, which is its inverted output, becomes 0. Furthermore, inverters 35b and 35c
After that, the output of the inverter 35d becomes 0, so
Again, the P2 output of the C element 34 is 0, an inverted output.
P1 output becomes 1. As the P1 output of this C element 34 becomes 0 and then becomes 1, the C element 7i
P2 output becomes 1 and becomes 0, and the C element 7i
returns the received Pl output to the previous stage C element 7h, sends the P2 output to the next stage C element 7j, transmits one word of data to the next stage, and in this way operates the momentary switch 39. Thus, data is transmitted word by word. In the device of this embodiment as described above, the output timing of P2 and P1 of the C element is controlled by the transfer timing control circuit, so that the data is
Words can be separated and propagated, and as a result, when an arithmetic processing unit is constructed using this device, it becomes possible to observe various states of various functional components in small sections. In the above embodiment, the C element has a two-stage structure, but it may have a one-stage structure as shown in FIG. Furthermore, although the above embodiment describes a case in which data is transmitted between asynchronous systems, the present invention can be similarly applied to a case in which data is transmitted between synchronous systems, and in this case, the C element is used as a synchronous control circuit. Bye. Further, the C element used in the above-mentioned asynchronous self-propelled shift register has a configuration different from the C element (hereinafter referred to as the first type C element) 7 shown in FIG. 3, for example, the second type C element shown in FIG. 8a. It may be the C element 50 or the third type C element 51 shown in FIG. 8b. In FIG. 8a, the second type C element 50 is a two-stage configuration of the first type C element 7, and in FIG. 8b, the third type C element 51 is composed of two-input NAND gates 52a, 52b, 52c, a negative logic input OR gate 53, and an inverter 54. [Effects of the Invention] As described above, according to the present invention, in a data transmission device in which a data transmission path is configured using an asynchronous free-running shift register consisting of a data latch and a C element, The output timing of one C element is controlled by the transfer timing control means in response to the data transfer timing instruction from the instruction means for instructing the data transfer timing, so that data can be propagated slowly when necessary. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is an overall block diagram of a data transmission device developed by the applicant, and FIGS. 3 and 4 are both used in the above device. FIG. 5 is a diagram for explaining the functions of this asynchronous self-propelled shift register, and FIGS. 6 and 7 are specific diagrams of the above-mentioned device. FIGS. 8a and 8b are circuit diagrams showing examples of other C elements used in the present invention. 5...Data transmission line, 6...Parallel data latch, 7...C element (transfer control circuit), 30...Transfer timing control circuit (transfer timing control means), 39...Momentary switch (instruction means).
In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. An asynchronous free-running shift register consisting of a plurality of data storage means and a transfer control circuit in each stage that controls the data storage means in its own stage according to a control signal from a transfer control circuit in an adjacent stage. In a data transmission device that is provided with a data transmission path constructed using the above data transmission path and that performs data transmission between systems using the data transmission path, an instruction means for instructing the timing of transferring data for each stage of the data storage means; A data transmission device comprising: transfer timing control means for controlling output timing of a control signal of one of the transfer control circuits according to an output of the instruction means.