JPH0445009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a NOT circuit used in Josephson logic circuits and Josephson memory circuits.

(Prior art) When configuring a logic circuit using Josephson circuits,
As in the case of constructing logic circuits using conventional silicon technology, generation of a negation signal is essential. However, Josephson's logic circuit has a drawback in that the signal amplification factor is small, so the latch operation is the main operation, and it is difficult to construct an inverting circuit.

Conventionally, as a circuit that generates a complementary signal to an input signal, there is a circuit that generates a complementary signal to an input signal.
development), Vol. 24, No. 2, p. 139, and the inverter circuit, which was published in April 1982, as a negative circuit consisting only of resistors and Josephson junction elements, excluding inductance. 1981 IEICE General Conference National Conference Proceedings, Volume 2, No. 2-448 Pages Timed Inverter
NOR logic circuits are known.

As shown in FIG. 5, the timed inverter circuit has two inductances 511 to 511, respectively.
514 and two Josephson junction elements 521-5
This is a circuit in which two 2-junction squid transistors 501 and 502 consisting of 24 transistors are switch gated and connected in series. A gate current is injected into the two two-junction squids 501 and 502 via a terminal 544. A data signal to be negated is applied from a terminal 541 to the first two-junction squid 501.
A timing signal for generating a negative signal is input to the second two-junction squid 502 from a terminal 542. The output signal is taken out from the output terminal 543 via the load resistor 532.

The inverter circuit operates as follows.

1 Data signal “1” is 2-junction squid 501
The two-junction squid 501 switches, and most of the gate current flows into the load resistor 531. Even if a timing signal is then input to the 2-junction squid 502, the 2-junction squid 502 does not switch because almost no gate current flows through the 2-junction squid 502. Therefore, no output current appears at the output terminal 543. That is, "0" is output.

2 Data signal “0” is 2-junction squid 501
is input. At this time, 2-junction squid 50
1 is not switched and the gate current continues to flow through the two-junction squid 502. Subsequently, when the timing signal is input to the two-junction squid 502,
The two-junction squid 502 switches and an output current, or "1", appears at the output terminal 543.

In the manner described above, a complementary signal of the input data signal is generated.

FIG. 6 shows a conventional timed inverter NOR logic circuit. This circuit consists of Josephson junction elements 601-607 and resistors 611-607.
618, input resistors 619 and 620, and a load resistor 621. A data signal is input to a data signal input terminal 631, and a timing signal is input to an input terminal 632. Gate current is injected from terminal 634.

Operation when data signal “1” is input When data signal “1” is input, Josephson junction elements 601 and 602 switch in sequence. By switching the Josephson junction elements 601 and 602, the gate current is changed to the Josephson junction element 60.
6 and switches Josephson junction 606. Josefson junction element 601, 602, 6
06, the gate current flows into the load resistor 621 and the Josephson junction element 603.
~605, current stops flowing.

A timing signal is input to input terminal 632 with a delay from the data signal. At this time, since almost no gate current flows through the Josephson junction elements 603 to 605, the Josephson junction elements 603 to 605
3 to 605 do not switch. Due to the above operation, no output appears at the output terminal 633. That is, a complementary signal "0" of the data signal "1" is output.

Operation when data signal “0” is input Data signal “0” means that the signal current is zero. Therefore, the data signal “0” is input to the input terminal 631.
Even if input to Josephson junction elements 601-6
The state of 05 remains unchanged. That is, the gate current continues to flow through the Josephson junction elements 601-605.

Subsequently, when a timing signal is input to input terminal 632, Josephson junction elements 603-605 are switched. Josefson junction element 603-6
05 causes gate current to flow into Josephson junction devices 606 and 607, switching both gates. Josephson junction element 601
The gate current flows to the output terminal 633 by the switch 607, and an output signal "1" is obtained. That is, a complementary signal "1" of the data signal "0" is output.

(Problems to be Solved by the Invention) In the conventional timed inverter circuit shown in FIG. 5, the switch gate was constructed from a squid consisting of an inductance and Josephson junction element. Therefore, there is a drawback that the area of the negative circuit cannot be reduced in order to realize a desired inductance value. That is, if the Squid inductance is L and the gate current value used for logic is I, LIΦ ₀ /2 (Φ ₀ represents the magnetic flux quantum, Φ ₀
= 2.07×10 ^-15 Weber). Therefore, when the logic current I is reduced in order to reduce power consumption, L becomes larger and larger, making it even more difficult to reduce the circuit area. Furthermore, an increase in circuit area results in an increase in signal transmission time, which has been an obstacle to increasing the speed of logic circuits and memory circuits.

On the other hand, conventional timed inverter NOR logic circuits consist only of resistors and Josephson junction elements, excluding inductance, so it is possible to reduce the circuit area and increase the speed of the circuit, but it is necessary to separate the input and output signals. Since Josephson junction element 607 is grounded via input resistor 620, there is a drawback that the operating margin is narrow for the following reason. That is, as described above, when the data signal is "0", after the Josephson junction elements 603 to 605 are switched, the Josephson junction elements 606 and 607 are switched.
switches. In this case, a wider operating margin can be obtained under the condition that Josephson junction element 606 is switched first. However, even in the case where Josephson junction element 606 is switched first, the gate current is
7. Since the current is shunted to ground via the input resistor 620, the gate current injected into the Josephson junction element 606 is reduced, and the lower limit of the operating margin becomes large, narrowing the operating margin of the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current-limited Josephson resistor-coupled inverter that eliminates the drawbacks of the conventional Josephson inverter described above, reduces the area, increases the speed of circuit operation, and provides a wide operating margin. be.

(Means for Solving the Problems) A current-limited Josephson resistance-coupled inverter according to the present invention includes at least one first switch Josephson junction element having a gate current injection end and a gate current extraction end; is connected to the injection end and the other end is connected to a first signal input terminal; an input resistor connected between the first signal input terminal and ground; a first Josephson logic circuit including a load resistor connected to an injection end; at least one second Josephson junction element having a gate current injection end and a gate current exit end; A current-limiting Josephson junction element connected to the injection end of the Josephson junction element for the second switch, the other end of which is connected to the second signal input terminal, and the injection end and output terminal of the Josephson junction element for the second switch. a second Josephson logic circuit including a load resistor connected thereto, no input resistor is connected between the second signal input terminal and ground, and at least one of the first Josephson logic circuits The outlet end of the first Josephson logic circuit is connected to the first Josephson logic circuit so that the switch junction element and at least one switch junction element of the second Josephson logic circuit are directly connected in series without using a resistor. The second Josephson logic circuit is connected to the injection end of the second Josephson logic circuit, and the outflow end of the second Josephson logic circuit is grounded.

(Function) FIG. 1 shows the basic configuration of a Josephson resistance-coupled negation circuit for explaining the principle of the present invention.

The current limiting type Josephson resistive coupling inverter of the present invention includes a Josephson junction element 10 for a switch.
1 and 102 are directly connected in series without using a resistor, and the input/output separation Josephson junction element 1 is connected to the gate current injection end of the Josephson junction element 101 for a switch.
03 is connected to an input resistor 111, and a data signal is input from a first signal input terminal 121. Resistor 112 is a load resistance. A current limiting Josephson junction element 104 is connected between the gate current injection end of the second switch Josephson junction element 102 and the second signal input terminal 122 . Second
The input resistance between the signal input terminal 122 and ground is removed. The timing signal is input from the second signal input terminal 122. The output signal is taken out from the output terminal 123 via the load resistor 113.

Here, Josephson junction elements 101, 103
and resistors 111 and 112 constitute a first Josephson logic circuit. Similarly, Josephson junction elements 102, 104 and resistor 113 constitute a second Josephson logic circuit. The first Josephson logic circuit is switched by a data signal input to the first signal input terminal 121, and the second Josephson logic circuit is switched by the data signal input to the first signal input terminal 22.
It is switched by a timing signal input to the

(First Embodiment) The current-limited Josephson resistance-coupled inverter circuit shown in FIG. 1 actually operates as the first embodiment of the present invention. Below, based on Figure 1,
The circuit operation of this embodiment will be explained.

Generation of complementary signal of data signal “1”: Data signal “1” is connected to the first signal input terminal 121
, the first switching Josephson junction element 101 switches. The switching of the Josephson junction device 101 causes the gate current to flow towards the input/output isolation Josephson junction device 103, causing the Josephson junction device 103 to switch. Most of the gate current is transferred to the load resistor 112 due to the switch of Josephson junction elements 101 and 103.
flows to Therefore, the current flowing through the Josephson junction element 102 for the second switch becomes almost zero.

Next, a timing signal is input from the second signal input terminal 122. The timing signal flows into the Josephson junction element 102 for switching, but since almost no gate current flows through the Josephson junction element 102, it does not switch. Therefore, no output signal appears at the output terminal 123. That is, a data signal "0" which is a complementary signal of input data "1" is obtained.

Generation of complementary signal of data “0”: Data “0” is input to the first signal input terminal 121. A signal "0" means that the input current is zero. Therefore, the Josephson junction element 101 for the first switch does not change at all, ie, does not switch. Therefore, the gate current continues to be injected from the Josephson junction element 101 to the Josephson junction element 102 for the second switch.

Next, a timing signal is input to the second signal input terminal 122. Since a gate current is flowing through the second switching Josephson junction element 102, the Josephson junction element 102 is switched by the inflow of the timing signal. The switch in Josephson junction device 102 shunts most of the gate current to input/output isolation Josephson junction 103. The gate current diversion ratio is determined by the resistance value _r1 of the input resistor 111 and the resistance value of the load resistors 112 and 113.
It depends on r ₂ , r ₃ and the current value It of the timing signal.
The critical current value aIo of the input/output separation Josephson junction element 103 is as described below based on FIG.
The shunted gate current value can be selected below,
Josephson junction element 103 switches. Therefore, the gate current is equal to the load resistance 112 and the load resistance 1.
13 and flows separately. Therefore, the output terminal 123 receives a signal “1” which is a complementary signal of the data signal “0”.
is output.

As described above, the circuit of this embodiment generates a complementary signal of the data signal inputted to the first signal input terminal 121 using the timing signal inputted to the second signal input terminal 122, and generates a complementary signal of the data signal inputted to the first signal input terminal 121, and Output to.

FIGS. 2a and 2b show the threshold characteristics of this embodiment when the critical current value of Josephson junction elements 101 and 102 for switches is Io. The vertical axis of the figure indicates the gate current value Ig injected into the terminal 124, and the horizontal axis indicates the input terminal 122, 12.
1 shows a timing signal current It and a data signal current Id, respectively. In the figure, gate current Ig, data signal current Id, timing signal current
Josephson junction element 101 for it and switches,
It is shown normalized by a critical current value Io of 102.
Figure 2 a shows the gate current Ig and timing signal current.
FIG. 2b shows the relationship between the gate current Ig and the data signal current Id.

First, the operating threshold value when a timing signal is input after a data signal "0" is input will be explained.

A threshold value 201 indicates a critical current value bIo of the current limiting Josephson junction element 104. A timing signal current It greater than bIo is not injected into the second switch Josephson junction element 102 through the current limiting Josephson junction element 104.

A threshold value 202 is a threshold value at which the gate current Ig and the timing signal It are added to switch the second Josephson junction element 102 for switching.
This shows Ig+It≧Io. Since It greater than bIo is not injected into Josephson junction element 102,
The threshold value 202 is constant in the region It>bIo where the timing signal current is larger than the intersection with the threshold value 201.
Ig≧(1-b)Io.

The threshold value 203 indicates a threshold value Ig+It≧a(1+r ₁ /r ₃ +r ₄ ))Io at which the input/output separation Josephson junction element 103 switches after the second switching Josephson junction element 102 switches. It is something. This is input resistance r ₁ , load resistance r ₂ ,
r ₃ , critical current value of Josephson junction element 103
Varies depending on aIo. The threshold value 204 indicates the condition Ig<Io under which the Josephson junction elements 101 and 102 for switching do not switch with only the gate current.

In the above conditional expression, the nonlinear resistance of Josephson junction elements 101 to 103 is determined by each resistance value r ₁ ,
It is assumed that r ₂ and r ₃ are sufficiently large, and is omitted from the calculation formula for simplicity. More precisely, each threshold value is determined taking into account the nonlinear resistance.

Next, the data signal “1” is applied to the first signal input terminal 1.
The operation when a timing signal is input after input to 21 will be explained. Since the critical current value of the input/output separation Josephson junction element 103 is aIo,
A threshold 211 similar to threshold 201 is obtained.

The threshold value at which the first switching Josephson junction element 101 switches due to the current Id of the data signal is Ig+Id>Io in the region Id≦aIo, and constant Ig≧(1-a)Io in the region Id>aIo. threshold 212
is obtained.

Next, input/output separation Josephson junction element 103
The threshold value for switching becomes the threshold value 213 when Ig≧(1+r ₁ /r ₂ )aIo +r ₁ /r ₂ Id. Most of the gate current flows to the load resistor 112 by switching the Josephson junction elements 101 and 103, and the Josephson junction element 102 does not switch even if the timing signal It is input. The maximum value of the gate current Ig flowing through the Josephson junction element 101 satisfies Ig<Io, and a threshold value 214 matching the threshold value 204 is obtained.

Above, threshold values 202, 204, 212 to 21
4, the diagonally shaded areas 221 and 22 in FIG.
2 is the operating region of this embodiment. Considering more precisely the effect of the nonlinear resistance of Josephson junction elements, the operating regions 221 and 222 are somewhat reduced.
What is particularly problematic here is the effect of the load resistance _r2 . In the operation of the first Josephson logic circuit shown in Figure 2a, the load resistance r ₂ is Vg/Ig (Vg
is set larger than the gap voltage of the Josephson junction element), Ig-Vg/ _r2 leaks to the Josephson junction element 102.

Due to this leakage current and the subsequently input timing signal current, the conditions under which the Josephson junction element 102 for switch does not switch are Ig-Vg/
r ₂ +It<Io. The threshold value 205 is based on this condition.
It shows Ig+It<Io+Vg/ _r2 . In the figure, threshold 205 and threshold 201 are Ig
>They intersect in the Io area. Here, threshold 2
01 indicates that It=bIo in the region It>bIo, so the threshold value 205 in the region It>bIo does not affect the operating characteristics. That is, the threshold value 2 is placed at the intersection of the threshold value 201 and the threshold value 204.
05 is the condition under which the threshold value 205 gives the maximum r ₂ without affecting the operating characteristics. Therefore, by setting the load resistance r ₂ such that r ₂ <Vg/bIo, the effect of the leakage current on Josephson junction element 102 can be eliminated.

As described above, according to the simplest embodiment consisting of four Josephson junction elements and three resistors, a negative signal can be generated with a sufficient operating range. According to this embodiment, the number of circuit elements is significantly reduced, and since no inductance is used as a circuit element, the circuit area can be greatly reduced.
Further, the second Josephson logic circuit has a current-limiting Josephson junction, but the input resistance is removed, so that the operating range is expanded. On the other hand, the first Josephson logic circuit also has the effects of the present invention as described below. That is, since the first and second Josephson junction elements for the switch are directly connected in series without using a resistor, the voltage at the injection end of the Josephson junction element for the first switch is zero in the initial state. . Therefore, all the gate current flows toward the Josephson junction element for the switch and does not leak to the input/output separation Josephson junction 103, so that the operating margin is expanded.

Note that there is no problem in eliminating the input resistance of the second Josephson logic circuit because of the way the NOT circuit is used. That is, the timing signal input to the second Josephson logic circuit is input to all the NOT circuits in parallel. Also, from the threshold characteristics shown in Figure 2b,
Timing signal currents greater than bIo do not affect the operation of the inverter. This means that even if the timing signal current It flowing into another NOT circuit increases due to a load change in a certain NOT circuit, the operating range of the other designated circuits will not be affected at all. Furthermore, the timing signal is inputted to all the NOT circuits at once, causing each NOT circuit to operate simultaneously. In addition, since the switching operation of the first Josephson logic circuit caused by the data signal does not affect the second signal input terminal, noise flows from the inverting circuit into the previous stage timing signal generation circuit, causing the previous stage circuit to be damaged. No failure modes occur that cause a switch.

(Second Embodiment) FIG. 3 shows a second embodiment in which two Josephson junction elements for a switch are connected in parallel.

Josephson junction elements 301 and 302 for the first switch of the first logic circuit are connected to resistors 311 to 31.
Josephson junction elements 303, 3 for the second switch of the second logic circuit are connected in parallel via 4;
04 are connected in parallel via a resistor 314. Input/output separation Josephson junction 305 current limiting Josephson junction element 306, input resistance 315,
Load resistors 316 and 317 function in the same way as in the first embodiment. The resistors 311, 312, 313 are
This resistor is used to shunt the gate current Ig injected from the terminal 324 to the Josephson junction elements 301 and 302.

The threshold characteristics of the operation of the circuit of this embodiment are shown in FIGS. 4a and 4b. In Fig. 4a, the data signal is “0”
When the timing signal is input to the first signal input terminal 3
This is the threshold characteristic of the gate current Ig and the timing signal current It when inputted to 22. Figure 4b is
Gate current Ig and data signal current Id when data signal “1” is input to the first signal input terminal 321
is the threshold characteristic of Here, the critical current value of Josephson junction elements 301 to 304 for switches is:
All are set to Io, and each axis in Figure 4 is normalized to Io.

First, the operation when a timing signal is input after a data signal "0" is input will be described.

The critical current value of current limiting Josephson junction device 306 is indicated by threshold 401 in bIo. Adding the gate signal Ig and the timing signal current It,
The threshold value for switching the Josephson junction element 303 for the second switch is in the region of It≦bIo.
A threshold value 402 for Ig/2+It≧Io, and a threshold value 40 for a constant Ig≧2(1-b)Io in the region of It>bIo.
It can be expressed as 7. Once Josephson junction element 303 switches, Josephson junction element 304 subsequently switches. Next, the threshold value at which the input/output separation Josephson junction element 305 switches is determined by the first
Same as the example of Ig+It>a(1+r ₁ /(r ₂ +r ₃ ))
Io, and is indicated by a threshold value 403. The threshold value 405 is determined by Josephson junction elements 303 and 304.
Conditions where Ig<2Io does not switch due to gate current only
It is. Here, the value of the resistor 314 is selected to be a small value such that the Josephson junction elements 301 and 302 are not switched by the switch of the Josephson junction element 303.

Next, the operation when the timing signal is input after the data signal "1" is applied will be explained with reference to FIG. 4b. The circuit operation at this time is similar to that of the first embodiment.

A threshold value 411 indicates a critical current value aIo of the input/output separation Josephson junction element 305. The conditions for the switch Josephson junction element 301 to switch are a threshold value 412 that satisfies Ig/2+Id≦Io in the region of Id≦aIo, and a threshold value 412 that satisfies Ig≧2(1−a) in the region of Id>aIo.
It is indicated by a threshold value 415 which is Io. Threshold 4
13 is an input/output separation Josephson junction element 305
The threshold value 414 indicates the condition Ig≧(1+r ₁ r ₂ )aIo+r ₁ /r ₂ Id) in which the switch is switched. There is. Due to the effect of the load resistance r ₂ , the condition that the Josephson junction element 303 for switching does not switch when the data signal "1" is input and the timing signal is input is (Ig - Vg / r ₂ ) x 0.5 + It < Io. Figure 4a
is indicated by a threshold value 406. Threshold 4 of this condition is set at the intersection of threshold 401 and threshold 405.
The value of load resistance r ₂ when crossing 06 is r ₂ =
Vg/2bIo. That is, by selecting r2<Vg/2bIo, the effect of load resistance _r2 can be removed. Note that the resistors 311 to 314 are set to be sufficiently smaller than the input resistance _r1 .

As described above, the operating range of the circuit of the second embodiment includes the threshold values 402, 405, 407, the threshold value 412,
Area 4 indicated by diagonal lines surrounded by 414 and 415
It becomes 21,422. In this embodiment, the threshold values 403, 404, and 413 have little effect on the operating range. This is because a second Josephson junction element for the switch is connected in parallel and the maximum allowable gate current is doubled, so the operating range of this embodiment is significantly expanded compared to the first embodiment. It is shown that.

A configuration in which the number of Josephson junction elements for switches in parallel in the second embodiment is three or more is also included as another embodiment of the present invention.

In the circuit of the present invention, Josephson junction elements for switches are connected without using a resistor in between.
Gate current does not flow to the data signal input terminal side.
Therefore, the operation of the circuit that generates the data signal is not affected, and the circuit that generates the data signal does not malfunction.

As described above, in the circuit of the present invention, the second signal input terminal is not grounded via a low impedance resistor. Therefore, the current-limiting Josephson junction device does not have the input/output isolation function that the input/output separating Josephson junction device of the conventional resistance-coupled logic circuit has. Even in the case where the timing signal applied to the NOT circuit is used to drive a large number of NOT circuits as a load for the preceding stage drive circuit, input/output separation is problematic due to the general usage of NOT circuits, as described above. Not. This is because when the second signal input terminals of a large number of NOT circuits are connected in parallel as loads of the previous stage drive circuit, each NOT circuit is switched by the switch of the previous stage drive circuit, but This is because the previous stage drive circuit is not switched by this switch. That is, the operation margin in which the switching Josephson junction element of the present NOT circuit switches without inputting a timing signal is sufficiently larger than the operation margin of the NOT circuit. Furthermore, after all the circuits are switched on,
Even if load fluctuation noise is transmitted from the output side to the input side, it will not be a problem because all the negative circuits are switched.

(Effects of the invention) As described above, according to the present invention, a negative circuit without inductance, which is conventionally used in a negative circuit, is realized, and the disadvantage that the circuit area cannot be reduced due to the inductance value is eliminated, and the circuit can be made smaller. . Furthermore, the speed of the circuit can be increased by reducing the signal transmission delay due to the miniaturization of the circuit. By eliminating the conventional control of the Josephson junction element switch by magnetic field coupling, even higher speeds can be achieved. moreover,
Efforts are also being made to expand the operating margin.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the circuit of the present invention for explaining the principle of the present invention, and FIG. 2 is a diagram showing the threshold characteristics of the circuit of the first embodiment.
Figure a shows the relationship between timing signal current It and gate current Ig, and Figure 2 b shows the relationship between data signal current Id and gate current Ig.
3 is a circuit diagram showing the second embodiment of the present invention, and FIG. 4 is a diagram showing the threshold characteristics of the circuit of the second embodiment. Figure 4a shows the relationship between the timing signal current It and the gate current Ig.
Figure b shows the relationship between data signal current Id and gate current Ig, Figure 5 is a circuit diagram of a conventional inverter circuit using two-junction squid, and Figure 6 is a diagram of a conventional timed inverter NOR logic circuit. It is a circuit diagram. 101, 102, 301-304... Josephson junction element for switch, 103, 305... Josephson junction element for input/output separation, 104, 306
...Current limiting Josefson junction element, 311~3
14...Resistance, 111,315...Input resistance, 1
12, 113, 316, 317...Load resistance, 1
21, 321...first signal input terminal, 122,
322...Second signal input terminal, 123, 323
... Output terminal, 124, 324 ... Gate current injection terminal, Ig ... Gate current, Id ... Data signal current, It ... Timing signal current, Io ... Critical current value of Josephson junction element for switch, 201 ~
205,211~214,401~407,41
1 to 415...Threshold value, 221, 222, 42
1,422...Operating area, 501,502...2
Junction squid, 511-514... Inductance, 521-524... Josephson junction element, 531, 532... Load resistance, 541... Data signal input terminal, 542... Timing signal input terminal, 543... Output terminal, 544 ... Gate current injection terminal, 601-607 ... Josephson junction element, 611-618 ... Resistor, 619,6
20...Input resistance, 621...Load resistance, 631
...Data signal input terminal, 632...Timing signal input terminal, 633...Output terminal, 634...
Gate current injection terminal.

Claims (1)

[Claims] 1 at least one Josephson junction element for a first switch having an injection end and a gate current exit end, and an input terminal having one end connected to the injection end and the other end connected to the first signal input terminal. a first Josephson logic circuit including an output isolation Josephson junction element, an input resistor connected between the first signal input terminal and ground, and a load resistor connected to the injection end; at least one second Josephson junction element for a switch having an injection end and an outlet end, one end connected to the injection end of the Josephson junction element for a second switch, and the other end connected to a second signal input; a second Josephson logic circuit including a current limiting Josephson junction element connected to a terminal, an injection end of the second switching Josephson junction element and a load resistor connected to an output terminal; No input resistor is connected between the input terminal and ground, and at least one Josephson junction element for a switch of the first Josephson logic circuit and at least one Josephson junction element for a switch of the second Josephson logic circuit. The outgoing end of the first Josephson logic circuit is connected to the injecting end of the second Josephson logic circuit such that the outgoing end of the first Josephson logic circuit is directly connected in series without using a resistor, and the outgoing end of the second Josephson logic circuit is connected in series without using a resistor. A current-limited Josephson resistor-coupled negation circuit characterized by grounding.