JPH0445063Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a start address generation circuit for outputting a start address to a microprogram memory in which microinstructions are stored in a microprogram control device. .

<Prior art> A microprogram control device has a
An example of a general microprogram control device is shown in FIG. 3, which sequentially reads microinstructions from a microprogram memory for each step to perform a predetermined operation.

The device shown in this figure has a pipeline register 1, is controlled by the timing of a control clock pulse CP, and outputs the output of a multiplexer 3 when a microinstruction I(A) is being executed for a controlled object 2. This is a device in which the microinstruction I (A+1) is read from the microprogram memory 5 by the next address A+1 from the input address sequencer 4 and stored in the pipeline register 1, and the microinstruction is being executed. The next microinstruction is read in parallel with the microinstruction.

FIG. 4 shows a start address generation circuit 6 for generating a start address, which is added to such a microprogram control device.

This start address generation circuit 6 is composed of a delay circuit ₆₁ and a buffer circuit ₆₂ to which a start address SA is applied, and an initialization signal
INZRST is input to the output control terminal of the address sequencer 4 via the delay circuit ₆₁ , and is also input to the enable terminal G of the buffer circuit ₆₂ .

Therefore, when the initialization signal INZRST is active "H", the address output Y of the address sequencer 4 becomes invalid, the buffer circuit ₆₂ is enabled, and the start address SA is given to the microprogram memory 5. On the other hand, if the initialization signal INZRST is inactive “L”,
The buffer circuit ₆₂ is disabled, the delay output of the initialization signal INZRST of the delay circuit ₆₁ is given to the address sequencer 4, and its address output Y is given to the microprogram memory 5.

Here, the phase relationship between the initialization signal INZRST and the control clock pulse CP is as shown in Figure 5 A and B, from when the initialization signal INZRST becomes inactive "L" until the control clock pulse CP rises. There is generally variation in the time ΔT of 1 microstep, and an appropriate delay constant for the delay circuit ₆₁ must be determined by taking into account the time T of 1 microstep and the variation in time ΔT. , was causing difficulties.

<Problem to be solved by the invention> The problem to be solved by the invention is to set the start address so that it operates independent of the phase difference between the initialization signal and the control clock pulse and the 1 microstep time. The purpose is to configure a generation circuit, and the purpose is to obtain a start address generation circuit with a simple configuration.

<Means for Solving the Problems> The present invention, which solves the above-mentioned problems, has a start address generation circuit that outputs a start address to a microprogram memory in which microinstructions are stored. a buffer circuit that directly supplies the data to the microprogram memory; a data terminal is always given an "H"level; a reset terminal receives an initialization signal; and a clock terminal receives a control clock pulse; when active, the output enables the buffer circuit and leaves the buffer circuit active when the initialization signal goes from active to inactive and the first rising edge of the control clock pulse does not occur; a D flip-flop circuit whose output disables the buffer circuit and enables the normal address sequencer when the initialization signal is inactive and the first rising edge of the control clock pulse occurs; This is a start address generation circuit.

<Operation> The start address generation circuit of the present invention selects the start address when the initialization signal is active, and selects the address at the rising edge of the control clock pulse when the initialization signal is inactive.
Switch to sequencer address output.

<Embodiment> FIG. 1 is a block diagram of a start address generation circuit embodying the present invention.

In this start address generation circuit 6,
D serves as a selection circuit that selects the start address SA and the address output of address sequencer 4.
A flip-flop circuit ₆₃ is used. The buffer circuit ₆₂ is the same as the conventional one shown in FIG.

In the D flip-flop circuit ₆₃ , the initialization signal INZRST is applied to the reset terminal RD, the control clock pulse CP is applied to the clock terminal CK, and the data terminal D is always provided with an "H" level. The terminal output is then applied to the output control terminal of the address sequencer 4 and the enable terminal G of the buffer circuit ₆₂ .

That is, when the output is "H", the address sequencer 4 output Y is disabled (high impedance state) and the output of the buffer circuit ₆₂ is enabled, and when the output is "L", the address sequencer 4 output Y is enabled and the buffer circuit 62 is enabled. Circuit 6 ₂ output is disabled.

Now, the operation of the start address generation circuit 6 of the present invention configured as described above is illustrated in FIG.
Explain using a time chart of c, d, ho, and f.

First, when the initialization signal INZRST is active "H", the output of the D flip-flop circuit ₆₃ is "H". Therefore, the output Y of the address sequencer 4 is invalid, the output of the buffer circuit ₆₂ is valid, and the output Y starts from the buffer circuit ₆₂ .
Address SA is applied to microprogram memory 5 and the corresponding microinstruction I(SA) is read.

Initialization signal INZRST is inactive “L”
If the first rising edge of the control clock pulse CP does not arrive, "L" is applied to the reset terminal RD of the D flip-flop circuit ₆₃ , but the output is "H" and the output of the microinstruction I (SA) is The read operation continues.

Initialization signal INZRST is inactive “L”
When the first rising edge of the control clock pulse CP arrives, the microinstruction I (SA) is set in the pipeline register 1 at this timing, and at the same time the Q output of the D flip-flop circuit ₆₃ goes "L". becomes. At this time, the buffer circuit ₆₂ is disabled and its output is disabled.
Address output Y (=A) of address sequencer 4
is applied to the microprogram memory 5, and the corresponding microinstruction I(A) is read out.

Thereafter, normal microprogram operations are performed.

In this way, the start address and the address output of the normal address sequencer are switched.

<Effects of the invention> The start address generation circuit of the invention selects the start address when the initialization signal is active, and selects the address at the rising edge of the control clock pulse when the initialization signal is inactive.
Since it switches to the address output of the sequencer, it is possible to configure a start address generation circuit that operates independently of the phase difference between the initialization signal and the control clock pulse and the 1 microstep time, making it easy to start the configuration. - An address generation circuit can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a start address generation circuit implementing the present invention, Figure 2 is a, b, c,
D, H and F are time charts for explaining the operation of the start address generation circuit of the present invention, Part 3.
4 is a block diagram of a conventional start address generation circuit, and FIGS. FIG. 3 is a pulse phase relationship diagram. 1... Pipeline register, 2... Controlled object, 3... Multiplexer, 4... Address sequencer, 5... Microprogram memory,
6...Start address generation circuit, ₆₁ ...Delay circuit, ₆₂ ...Buffer circuit, ₆₃ ...D flip-flop circuit.

Claims (1)

[Claims for Utility Model Registration] A start address generation circuit that outputs a start address to a microprogram memory in which microinstructions are stored, comprising: a buffer circuit that directly supplies a start address of a microprogram to the microprogram memory; , the data terminal is always given an "H" level, the reset terminal receives an initialization signal, and the clock terminal receives a control clock pulse, and when the initialization signal is active, its output enables the buffer circuit. and when the initialization signal changes from active to inactive and the first rising edge of the control clock pulse does not occur, the buffer circuit remains active, and when the initialization signal is inactive and the control clock pulse and a D flip-flop circuit whose output disables the buffer circuit and enables the conventional address sequencer when the first rising edge of a pulse occurs.