JPH0445200Y2

JPH0445200Y2 -

Info

Publication number: JPH0445200Y2
Application number: JP16276887U
Authority: JP
Priority date: 1987-10-23
Filing date: 1987-10-23
Publication date: 1992-10-23
Also published as: JPH0166700U

Description

【考案の詳細な説明】〔産業上の利用分野〕本考案はテストパターン書込み回路に関し、特
にＸ，Ｙの二次元アドレスを有する試験対象メモ
リへのテストパターン書込み回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a test pattern writing circuit, and particularly to a test pattern writing circuit to a memory under test having two-dimensional addresses of X and Y.

[Conventional technology]

第２図は試験対象メモリ上のテストパターンを
示すテストパターン表示図である。 FIG. 2 is a test pattern display diagram showing the test pattern on the memory under test.

従来、Ｘ，Ｙの二次元アドレスを有する試験対
象メモリのテストパターン、特にEPROMのテス
トパターンとして、第２図に示すように、最小ア
ドレスから最大アドレスまで交互に“０”（第２
図に●印で示す）と“１”（第２図に○印で示す）
にしたチエツカーパターンであるテストパターン
が使用されている。 Conventionally, as a test pattern for a memory under test having two-dimensional addresses of X and Y, especially an EPROM test pattern, "0" (second
(indicated by ● mark in the figure) and “1” (indicated by circle mark in Fig. 2)
A test pattern is used, which is a checker pattern.

このテストパターンをEPROMなどの試験対象
メモリに書込む従来のテストパターン書込み方式
は、このテストパターンを別途作成して用意し、
メモリテスタなどでその作成したテストパターン
を使用して、それを試験対象メモリへ書込む方法
を用いている。 In the conventional test pattern writing method, which writes this test pattern to the memory under test such as EPROM, this test pattern is created and prepared separately.
A method is used in which a test pattern created by a memory tester or the like is used and written to the memory to be tested.

[Problem that the invention attempts to solve]

上述した従来のテストパターン書込み方式は、
メモリテスタ内のメモリなどにテストパターンを
作成して用意しなければならないため、テストパ
ターンの作成に多大の工数と時間を必要とすると
いう問題点がある。 The conventional test pattern writing method described above is
Since test patterns must be prepared and prepared in the memory within the memory tester, there is a problem in that a large amount of man-hours and time are required to create the test patterns.

また、大容量のテストパターンの場合は、それ
が他のテストパターンなどとともにメモリテスタ
のメモリに入れておくことができないので、外部
に保管したテストパターンを使用時にメモリテス
タ内のメモリに移す必要があり、このために長い
時間がかかるという欠点もある。 In addition, in the case of a large-capacity test pattern, it cannot be stored in the memory tester's memory along with other test patterns, so it is necessary to transfer the test pattern stored externally to the memory within the memory tester when using it. However, the drawback is that it takes a long time.

本考案の目的は、チエツカーパターンであるテ
ストパターンを自動的に書くことができるテスト
パターン書込み回路を提供することである。 An object of the present invention is to provide a test pattern writing circuit that can automatically write a test pattern that is a checker pattern.

[Means for solving problems]

本考案のテストパターン書込み回路は、 (A) Ｘ，Ｙの二次元アドレスで選択される位置に
それぞれ２値信号を記憶でき、すべてのアドレ
スの情報を“１”にした当初の状態から、最小
アドレスから最大アドレスまでの情報を交互に
“０”と“１”にしたテストパターンを書込ん
だ最終の状態に推移する試験対象メモリ、 (B) 最小アドレスから最大アドレスまでを順々に
発生させて、それらのアドレスに情報“０”を
書込む動作を２回実行し、その第１回目の動作
中はＸアドレスの最下位ビツト線だけに平常の
“１”を示すアドレス信号より高い電圧を供給
し、その第２回目の動作中はＹアドレスの最下
位ビツト線だけに平常の“１”を示すアドレス
信号より高い電圧を供給するメモリテスタ、 (C) 前記メモリテスタのＸアドレスの最下位ビツ
ト線を接続して、前記第１回目の書込みで前記
メモリテスタからＸアドレスの最下位ビツト線
だけに供給される平常の“１”を示すアドレス
信号より高い供給電圧を検出して出力するＸ側
高電圧検出回路、 (D) 前記メモリテスタのＹアドレスの最下位ビツ
ト線に接続して、前記第２回目の書込みで前記
メモリテスタからＹアドレスの最下位ビツト線
だけに供給される平常の“１”を示すアドレス
信号より高い供給電圧を検出して出力するＹ側
高電圧検出回路、 (E) 前記Ｘ側高電圧検出回路に出力がある前記第
１回目の書込みでは、前記試験対象メモリのＸ
アドレスの最下位ビツト線に“０”を示す信号
を供給し、前記Ｙ側高電圧検出回路に出力があ
る前記第２回目の書込みでは、前記試験対象メ
モリのＸアドレスの最下位ビツト線に“１”を
示す信号を供給するＸ側最下位信号供給回路、 (F) 前記Ｘ側高電圧検出回路に出力がある前記第
１回目の書込みでは、前記試験対象メモリのＹ
アドレスの最下位ビツト線に“０”を示す信号
を供給し、前記Ｙ側高電圧検出回路に出力があ
る前記第２回目の書込みでは、前記試験対象メ
モリのＹアドレスの最下位ビツト線に“１”を
示す信号を供給するＹ側最下位信号供給回路、を備えて構成されている。 The test pattern writing circuit of the present invention is capable of storing binary signals at the positions selected by (A) two-dimensional addresses of X and Y, and from the initial state where the information of all addresses is The memory under test changes to the final state in which a test pattern is written in which information from the address to the maximum address is alternately set to "0" and "1"; (B) The memory to be tested changes to the final state in which the information from the minimum address to the maximum address is generated in sequence Then, the operation of writing information “0” to those addresses is executed twice, and during the first operation, a voltage higher than the address signal that normally indicates “1” is applied to only the lowest bit line of the X address. (C) A memory tester that supplies a voltage higher than the address signal normally indicating "1" only to the lowest bit line of the Y address during the second operation; (C) the lowest bit line of the X address of the memory tester; Connect the bit lines and detect and output a supply voltage higher than the normal address signal indicating "1" which is supplied from the memory tester only to the lowest bit line of the X address during the first write. side high voltage detection circuit, (D) connected to the lowest bit line of the Y address of the memory tester to detect a normal voltage that is supplied from the memory tester only to the lowest bit line of the Y address in the second write; (E) a Y-side high voltage detection circuit that detects and outputs a supply voltage higher than the address signal indicating "1"; X of
In the second write, in which a signal indicating "0" is supplied to the lowest bit line of the address and an output is output to the Y-side high voltage detection circuit, "0" is supplied to the lowest bit line of the X address of the memory under test. (F) An X-side lowest signal supply circuit that supplies a signal indicating "1";
In the second write, in which a signal indicating "0" is supplied to the lowest bit line of the address and an output is output to the Y-side high voltage detection circuit, "0" is supplied to the lowest bit line of the Y address of the memory under test. The Y-side lowest signal supply circuit supplies a signal indicating "1".

〔Example〕

次に本考案の実施例について図面を参照して説
明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本考案の一実施例のブロツク図であ
る。 FIG. 1 is a block diagram of one embodiment of the present invention.

第１図の試験対象メモリ１は、Ｘ，Ｙの二次元
アドレスで選択される位置にそれぞれ２値信号を
記憶でき、すべてのアドレスの情報を“１”にし
た当初の状態で製造されているので、この試験対
象メモリ１を最小アドレスから最大アドレスまで
の情報が交互に“０”と“１”であるテストパタ
ーンを書込んだ最終の状態にする動作が以下に説
明するように行われる。 The test target memory 1 shown in Fig. 1 can store binary signals in the positions selected by the two-dimensional addresses of X and Y, and is manufactured in the initial state in which the information at all addresses is set to "1". Therefore, the operation of bringing the memory 1 under test into the final state in which a test pattern in which the information from the minimum address to the maximum address is alternately "0" and "1" is written is performed as described below.

まず、メモリテスタ２は、最小アドレスから最
大アドレスまでを順々に発生させ、それらのアド
レスに情報“０”を書込む動作を２回実行する
が、その第１回目の動作中はＸアドレスの最下位
ビツト線A_X0だけに平常の“１”を示すアドレス
信号の電圧5Vより高い電圧9Vを供給し、その第
２回目の動作中はＹアドレスの最下位ビツト線
A_Y0だけに平常の“１”を示すアドレス信号の電
圧5Vより高い電圧9Vを供給する。 First, the memory tester 2 sequentially generates addresses from the minimum address to the maximum address and executes the operation of writing information "0" to those addresses twice. During the first operation, the A voltage of 9V, which is higher than the normal voltage of 5V for the address signal indicating "1", is supplied only to the lowest bit line A _X0 , and during the second operation, the lowest bit line of the Y address
A voltage of 9V, which is higher than the voltage of 5V of the address signal that normally indicates "1", is supplied only to A _Y0 .

Ｘアドレス最下位回路X₀にあるＸ側高電圧検
出回路３は、メモリテスタ２のＸアドレスの最下
位ビツト線A_X0に接続しており、第１回目の書込
みでメモリテスタ２からＸアドレスの最下位ビツ
ト線A_X0だけに供給される平常の“１”を示すア
ドレス信号の電圧5Vより高い供給電圧9Vを検出
して“１”を示す信号を出力する。 The X side high voltage detection circuit ₃ in the lowest X address circuit _X0 is connected to the lowest bit line A It detects a supply voltage of 9V, which is higher than the voltage 5V of the address signal which normally indicates "1" and is supplied only to the lowest bit line A _X0 , and outputs a signal indicating "1".

一方、Ｙアドレス最下位回路Y₀にあるＹ側高
電圧検出回路４は、メモリテスタ２のＹアドレス
の最下位ビツト線A_Y0に接続しており、第２回目
の書込みでメモリテスタ２からＹアドレスの最下
位ビツト線A_Y0だけに供給される平常の“１”を
示すアドレス信号の電圧5Vより高い供給電圧9V
を検出して“１”を示す信号を出力する。 On the other hand, the Y side high voltage detection circuit 4 located at the lowest Y address circuit _Y0 is connected to the lowest bit line A _Y0 of the Y address of the memory tester 2, and the Y side high voltage detection circuit 4 is connected to the lowest bit line A Y0 of the Y address of the memory tester 2. Supply voltage 9V higher than the voltage 5V of the address signal indicating normal “1” supplied only to the lowest bit line A _Y0 of the address
is detected and outputs a signal indicating "1".

これらにより、Ｘアドレス最下位回路X₀にあ
るＸ側最下位信号供給回路５は、Ｘ側高電圧検出
回路３に出力がある第１回目の書込みでは、“１”
を示すＸ側高電圧検出回路３の出力が否定回路を
通つて“０”になり、これが論理積回路の入力に
供給されるので、論理積回路の否定出力である
a_X0は“１”を示し、さらに次の否定回路を通つ
た_X0は“０”を示すこととなり、試験対象メモ
リ１のＸアドレスの最下位ビツト線に“０”を示
す信号を供給する。 As a result, the X-side lowest signal supply circuit 5 at the X address lowest circuit X ₀ is "1" in the first write when the output is output to the X-side high voltage detection circuit 3.
The output of the X-side high voltage detection circuit 3, which indicates
a _X0 indicates "1", and _X0 which has passed through the next NOT circuit indicates "0", and a signal indicating "0" is supplied to the lowest bit line of the X address of the memory 1 under test.

また、Ｘ側最下位信号供給回路５は、Ｙ側高電
圧検出回路４に出力がある第２回目の書込みで
は、“１”を示すＹ側高電圧検出回路４の出力が
論理和回路を通つて“１”が論理積回路の入力に
供給され、他方で“０”を示すＸ側高電圧検出回
路３の出力が否定回路を通つて“１”が論理積回
路の入力に供給されるので、論理積回路の否定出
力である_X0は“０”を示し、さらに次の否定回
路を通つた_X0は“１”を示すこととなり、試験
対象メモリ１のＸアドレスの最下位ビツト線に
“１”を示す信号を供給する。 In addition, in the second write when the X-side lowest signal supply circuit 5 has an output to the Y-side high voltage detection circuit 4, the output of the Y-side high voltage detection circuit 4 indicating "1" passes through the OR circuit. Therefore, "1" is supplied to the input of the AND circuit, and on the other hand, the output of the , _X0 , which is the negation output of the AND circuit, shows "0", and _X0 that passes through the next negation circuit shows "1", and "1" is placed on the lowest bit line of the X address of memory 1 under test. ” is supplied.

一方、Ｙアドレス最下位回路Y₀にあるＹ側最
下位信号供給回路６は、Ｘ側高電圧検出回路３に
出力がある第１回目の書込みでは、“１”を示す
Ｘ側高電圧検出回路３の出力が否定回路を通つて
“０”になり、これが論理積回路の入力に供給さ
れるので、論理積回路の否定出力である_Y0は
“１”を示し，さらに次の否定回路を通つた_Y0は
“０”を示すこととなり、試験対象メモリ１のＹ
アドレスの最下位ビツト線に“０”を示す信号を
供給する。 On the other hand, the Y-side lowest signal supply circuit 6 located at the Y-address lowest circuit _Y0 is the X-side high voltage detection circuit that indicates "1" in the first write when the output is in the The output of 3 passes through the NOT circuit and becomes "0", which is then supplied to the input of the AND circuit, so _Y0 , which is the NOT output of the AND circuit, shows "1" and then passes through the next NOT circuit. Then, _Y0 indicates “0”, and Y0 of test target memory 1
A signal indicating "0" is supplied to the least significant bit line of the address.

また、Ｙ側最下位信号供給回路６は、Ｙ側高電
圧検出回路４に出力がある第２回目の書込みで
は、“１”を示すＹ側高電圧検出回路４の出力が
論理和回路を通つて“１”が論理積回路の入力に
供給され、他方で“０”を示すＸ側高電圧検出回
路３の出力が否定回路を通つて、“１”が論理積
回路の入力に供給されるので、論理積回路の否定
出力である_Y0は“０”を示し、さらに次の否定
回路を通つた_Y0は“１”を示すこととなり、試
験対象メモリ１のＸアドレスの最下位ビツト線に
“１”を示す信号を供給する。 In addition, in the second write in which the Y-side high voltage detection circuit 4 has an output, the Y-side lowest signal supply circuit 6 outputs the output of the Y-side high voltage detection circuit 4 indicating "1" through the OR circuit. "1" is supplied to the input of the AND circuit, and on the other hand, the output of the Therefore, _Y0 , which is the negation output of the AND circuit, shows "0", and _Y0 that passes through the next negation circuit shows "1", and " A signal indicating 1" is supplied.

なお、試験対象メモリ１のＸアドレスおよびＹ
アドレスの最下位ビツト線以外のすべてのビツト
線は、第１図にＮ−１桁目を示しているように、
メモリテスタ２の対応するＸアドレスおよびＹア
ドレスのビツト線にそれぞれ直結している。 In addition, the X address and Y address of memory under test 1
All bit lines other than the least significant bit line of the address are as shown in the N-1st digit in Figure 1.
They are directly connected to the corresponding X address and Y address bit lines of the memory tester 2, respectively.

第３図は第１回目の書込みで試験対象メモリ上
に書込まれる情報を示す書込みパターン表示図で
ある。 FIG. 3 is a write pattern display diagram showing information written on the test target memory in the first write.

上記の第１回目の書込みは、常に、試験対象メ
モリ１のＸアドレスおよびＹアドレスとともに最
下位ビツト線に“０”を示す信号を供給された状
態で、その他のアドレスビツト線の信号のすべて
の場合について、情報“０”を書込む動作を２度
行うので、第３図に示す●印の位置に情報“０”
を書込むこととなる。 In the first write described above, a signal indicating "0" is always supplied to the lowest bit line along with the X address and Y address of memory under test 1, and all the signals on the other address bit lines are In this case, the operation of writing information "0" is performed twice, so information "0" is written at the position marked with ● shown in Figure 3.
will be written.

また、第４図は第２回目の書込みで試験対象メ
モリ上に書込まれる情報を示す書込みパターン表
示図である。 Moreover, FIG. 4 is a write pattern display diagram showing information written on the test target memory in the second write.

上記の第２回目の書込みは、常に、試験対象メ
モリ１のＸアドレスおよびＹアドレスともに最下
位ビツト線に“１”を示す信号を供給された状態
で、その他のアドレスビツト線の信号のすべての
場合について、情報“０”を書込む動作を２度行
うので、第４図に示す●印の位置に情報“０”を
書込むこととなる。 The above second write is performed with a signal indicating "1" being supplied to the lowest bit line of both the X address and Y address of memory under test 1, and all the signals on the other address bit lines are In this case, since the operation of writing the information "0" is performed twice, the information "0" is written at the position marked with a circle in FIG. 4.

これら２回の書込み動作で、第３図に示す●印
の位置および第４図に示す●印の位置の両方に情
報“０”が書込まれるので、これらを合せて第３
図に示す●印の位置に自動的に情報“０”が書込
まれることとなる。 With these two write operations, information "0" is written to both the ● mark position shown in FIG. 3 and the ● mark position shown in FIG.
Information "0" will be automatically written in the position marked with ● in the figure.

なお、情報“０”が書込まれなかつた○印の位
置は、最初から情報“１”のままの状態にある。 It should be noted that the positions marked with ◯ where information "0" is not written remain as information "1" from the beginning.

この結果、最小アドレスから最大アドレスまで
交互に“０”と“１”にした第３図に示すチエツ
カーパターンであるテストパターンが自動的に書
込まれる。 As a result, a test pattern, which is a checker pattern shown in FIG. 3 in which "0" and "1" are alternately set from the minimum address to the maximum address, is automatically written.

[Effect of idea]

以上説明したように、本考案のテストパターン
書込み回路は、最小アドレスから最大アドレスま
で交互に“０”と“１”にしたチエツカーパター
ンであるテストパターンを自動的に書くことがで
きるという効果を有している。 As explained above, the test pattern writing circuit of the present invention has the effect of automatically writing a test pattern that is a checker pattern in which "0" and "1" are alternately set from the minimum address to the maximum address. have.

このため、テストパターンを別途作成して外部
に保管する手間が省け、使用時にメモリテスタ内
のメモリに移す時間も必要としないという効果が
ある。 This saves the effort of separately creating a test pattern and storing it externally, and also eliminates the need for time to transfer it to the memory within the memory tester when used.

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図、第２
図は試験対象メモリ上のテストパターンを示すテ
ストパターン表示図、第３図は第１回目の書込み
で試験対象メモリ上に書込まれる情報を示す書込
みパターン表示図、第４図は第２回目の書込みで
試験対象メモリ上に書込まれる情報を示す書込み
パターン表示図である。１……試験対象メモリ、２……メモリテスタ、
３……Ｘ側高電圧検出回路、４……Ｙ側高電圧検
出回路、５……Ｘ側最下位信号供給回路、６……
Ｙ側最下位信号供給回路、X₀……Ｘアドレス最
下位回路、Y₀……Ｙアドレス最下位回路。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a test pattern display diagram showing the test pattern on the test target memory, Figure 3 is a write pattern display diagram showing the information written to the test target memory in the first write, and Figure 4 is a write pattern display diagram showing the information written on the test target memory in the first write. FIG. 6 is a writing pattern display diagram showing information written onto the test target memory during writing. 1...Memory to be tested, 2...Memory tester,
3...X side high voltage detection circuit, 4...Y side high voltage detection circuit, 5...X side lowest signal supply circuit, 6...
Y side lowest signal supply circuit, X ₀ ... X address lowest circuit, Y ₀ ... Y address lowest circuit.

Claims

[Claims for Utility Model Registration] (A) Binary signals can be stored in the positions selected by the two-dimensional addresses of X and Y, and the minimum address (B) The memory under test transitions to the final state in which a test pattern in which information from the minimum address to the maximum address is written as "0" and "1" alternately. , executes the operation of writing information “0” to those addresses twice, and during the first operation, a voltage higher than the address signal that normally indicates “1” is supplied only to the lowest bit line of the X address. However, during the second operation, the memory tester supplies a voltage higher than the normal address signal indicating "1" only to the lowest bit line of the Y address; (C) the lowest bit line of the X address of the memory tester; The X side detects and outputs a supply voltage higher than the normal address signal indicating "1" which is supplied from the memory tester only to the lowest bit line of the X address during the first write by connecting the lines. (D) A high voltage detection circuit, which is connected to the lowest bit line of the Y address of the memory tester, and detects a normal " (E) A Y-side high-voltage detection circuit that detects and outputs a supply voltage higher than the address signal indicating "1"; X
In the second write, in which a signal indicating "0" is supplied to the lowest bit line of the address and an output is output to the Y-side high voltage detection circuit, "0" is supplied to the lowest bit line of the X address of the memory under test. (F) An X-side lowest signal supply circuit that supplies a signal indicating "1";
In the second write, in which a signal indicating "0" is supplied to the lowest bit line of the address and an output is output to the Y-side high voltage detection circuit, "0" is supplied to the lowest bit line of the Y address of the memory under test. 1. A test pattern writing circuit comprising: a Y-side lowest signal supply circuit that supplies a signal indicating "1".