JPH0445973U

JPH0445973U -

Info

Publication number: JPH0445973U
Application number: JP8674290U
Authority: JP
Priority date: 1990-08-21
Filing date: 1990-08-21
Publication date: 1992-04-20

Description

[Brief explanation of the drawing]

第１図ないし第３図は本考案に係わるゼロスパ
ン調整回路の一実施例を説明するために示したも
ので、第１図はゼロスパン調整回路の構成図、第
２図は補正値を求めるための説明図、第３図は補
正値算出の処理の流れ図、第４図及び第５図はそ
れぞれ従来のゼロスパン調整回路の構成図である
。２１……計測アンプ、２２……アナログデジタ
ル変換器、２３……識別信号発生スイツチ、２４
……ＣＰＵ、２５……プログラム可能ＲＯＭ。 Figures 1 to 3 are shown to explain one embodiment of the zero span adjustment circuit according to the present invention. Figure 1 is a configuration diagram of the zero span adjustment circuit, and Figure 2 is a diagram showing the configuration of the zero span adjustment circuit. The explanatory diagram, FIG. 3, is a flowchart of a process for calculating a correction value, and FIGS. 4 and 5 are configuration diagrams of a conventional zero span adjustment circuit, respectively. 21...Measuring amplifier, 22...Analog-digital converter, 23...Identification signal generation switch, 24
...CPU, 25...Programmable ROM.

Claims

[Scope of claim for utility model registration] After measuring the analog signal with a measurement amplifier, the CP
In the zero span adjustment circuit of a circuit that converts into a digital signal by an analog-to-digital converter controlled by U, the signal currently input to the analog-to-digital converter via the measurement amplifier is the upper limit of the reference voltage used for zero-span adjustment. a switch that generates a signal to identify whether the voltage is the current value or the lower limit value, and a correction value for zero span adjustment by taking in the upper and lower limit values of the reference voltage from the analog-to-digital converter based on the identification signal from this switch. A zero span adjustment circuit comprising: means for calculating a correction value to be obtained.