JPH0446059B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel operation power supply device, and particularly to a parallel operation power supply device in which a plurality of DC stabilized power supplies are connected in parallel.

[Conventional technology]

In large computers used in large-scale information processing systems, it may be necessary to supply a large current of several thousand amperes to one processing device. In such cases, a plurality of DC stabilized power supplies (hereinafter referred to as power supplies) are connected in parallel and used.

In such a usage method, it is necessary to detect the output currents of each power supply device in order to balance the output currents of each power supply device. However, since these output currents are also large currents exceeding 100 amperes, it is difficult to directly detect them. Therefore, a method is generally used in which a current transformer is inserted into the primary side of each power supply device and a voltage proportional to the output current on the secondary side is detected.

However, in this method, since the pulse width of the current transformer is constantly changing, it is difficult to accurately perform the above current balance by detecting its center value. In other words, conventional power supplies are only set to balance at a certain input voltage and output current.
The drawback is that if any of these is disturbed, the current balance will also be disrupted.

Further, overcurrent detection necessary for the power supply device can be performed using the output of the current transformer, but there is a drawback that the detection circuit for this must be manufactured using individual parts.

Furthermore, even if one of the power supplies fails during normal operation, it can be detected using the output of the current transformer, but there is a drawback in that the circuit for this must also be manufactured using individual parts.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, in other words, the purpose of the present invention is to provide a parallel operation power supply device that employs digital signal processing in order to eliminate the above-mentioned drawbacks peculiar to analog circuits.

[Means for solving problems]

In the parallel operation power supply device of the present invention, each of a plurality of DC stabilized power supply devices having a switching circuit is used as a slave module, and the plurality of slave modules are connected in parallel to each other to control each of them. In the parallel operation power supply device having a module, the master module includes a first AD converter that inputs the output voltage of the parallel operation power supply device and sends out digital data of the output voltage; The difference between the input digital data corresponding to a preset reference voltage and the digital data of the output voltage is sent out as voltage control data, and the output current data from each of the slave modules is input and their phases are controlled. a first microprocessor that sends out an average value as average current data and sends out a control signal for controlling data transmission and reception with each of the slave modules, and each of the slave modules
a second AD converter that inputs a voltage proportional to the output current of the module and sends digital data of the voltage as the output current data; inputs the output current data, the voltage control data, and the average current data; pulse width data obtained by correcting the voltage control data so that the difference between the output current data and the average current data becomes "0"; period data that sets a switching period of the switching circuit; and switching period data of the switching circuit.・Sampling control data of half the size of the pulse width data in order to sample the output current data at the center of the ON time of the pulse, and generating the switching pulse from the pulse width data and the period data. RST
a second microprocessor that sends a signal and an SP signal instructing sampling of the output current data; and inputs the periodic data and starts a switching operation of the switching circuit.
A rate generator that sends out the OUT1 signal in accordance with the RST signal, and an OUT2 signal that inputs the pulse width data and sets the switching pulse width of the switching circuit to the magnitude specified by the pulse width data. a programmable trigger that inputs the sampling control data and sends out an OUT3 signal that sets the sampling timing of the output current data in accordance with the sampling control data and the OUT2 signal;
A JK flip-flop which inputs the OUT1 signal and sends out the Q signal and the signal as a half-frequency divided signal of the OUT1 signal, and a JK flip-flop which inputs the OUT2 signal, the OUT3 signal, the Q signal and the signal and controls the switching operation of the switching circuit. and a gate circuit that sends a setting signal and an INT signal that instructs the second microprocessor to take in the output current data in accordance with the SP signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram including one embodiment of the parallel operation power supply device of the present invention. In the figure, a parallel operation power supply device 20 includes a master module 20a and three slave modules 21, 22, and 23. Master module 20
a is data bus 100, 101, 101a, 1
It transmits and receives control data to and from each slave module 21, 22, and 23 via 01b and 101c, and simultaneously sends out a control signal 110. The slave module 21 inputs the power input voltage E,
The output current I ₁ is sent out in accordance with the control signal 110 described above. Similarly, slave modules 22 and 23 also receive power input E and deliver output currents I ₂ and I ₃ respectively. These output currents I ₁ ,
I ₂ and I ₃ are condensed and supplied to the load device 30. Output voltage V ₀ is fed back to master module 20a. Note that even when there are four or more slave modules, the same configuration as above can be made.

Figure 2 shows the master module 20 shown in Figure 1.
FIG. 3 is a detailed block diagram of FIG. In FIG. 2, the master module 20a is the AD converter 11,
It consists of a microprocessor 12, an input buffer 13, and an output buffer 14. A.D.
The converter 11 inputs the above output voltage V ₀ ,
Send it as digital data. The microprocessor 12 transfers the digital data of the above output voltage _V0 to the data buses 102a, 10.
3a and 103b, compare it with digital data corresponding to a preset reference voltage, and calculate the difference as voltage control data.
Send as _VD .

In addition, the output current data In (n=1 to 3) of each slave module is transferred to the data bus 101, input buffer 13, data bus 102b, 103a.
and microprocessor 1 via 103b.
2, the microprocessor 12 calculates the arithmetic average value (I ₁ +I ₂ +I ₃ )/of the above output current data In.
3 is sent as average current data _IA .

Note that the voltage control data V _D and average current data I _A are transmitted through data buses 103b and 103a, output buffer 14, and data buses 104 and 10.
1.

Furthermore, the microprocessor 12 converts the DIRC signal, STRB signal and ATN signal into the control signal 11.
It is sent as 0 (details will be described later).

Figure 3 shows slave module 2 shown in Figure 1.
FIG. 1 is a detailed block diagram of FIG. In FIG. 3, the slave module 21 is composed of a converter section 15, a digital pulse width control section 16, and a driver section 17. The converter unit 15 is a DC-DC converter (details will be described later) having a switching circuit, and receives a power supply input voltage E and outputs a voltage _V2 for detecting an output voltage _V0 and output current data _I1 . do. The digital pulse width control unit 16 inputs the above voltage V ₂ and outputs the AD-converted output current data I ₁ to the data bus 101a.
and control pulses for driving the converter unit 15 according to the control signal 110, voltage control data V _D and average current data I _A
Send A1 and A2 (details will be described later). The driver section 17 receives the above control pulses A1 and A2 and sends out drive pulses B1 and B2 that directly drive the converter section 15. In addition, driver part 1
7 is usually constituted by a pulse transformer or the like.

FIG. 4 is a detailed circuit diagram of the converter section 15 shown in FIG. 3. In Figure 4, the transistor
Q1 and Q2 are turned on and off by drive pulse B1, and transistors Q3 and Q4 are turned on and off by drive pulse B2, respectively. For example, when transistors Q1 and Q2 are turned on, the power supply input voltage E causes a voltage V ₁ to be applied to the primary winding of pulse transformer T1.
and a current I ₁ occurs. Then, it is rectified and smoothed by the secondary winding of the pulse transformer T1, the diodes D1 and D2, the choke coil L1, and the capacitor C, and sends out a DC output voltage _V0 .
Similarly, when the transistors Q3 and Q4 are turned on, they are rectified and smoothed by the diodes D3 and D4, the choke coil L2, and the capacitor C, and send out a DC output voltage _V0 .

Current transformer T2 is turned on when transistors Q1 and Q2 or transistors Q3 and Q4 are ON.
When turned OFF, a current I _R is sent out through a rectifier circuit consisting of diodes D5 and D6 and a resistor R configured on the secondary winding side, and as a result, a voltage V ₂
=I _R・R is obtained. And current I ₁ flowing through the primary winding of current transformer T2 due to this voltage V ₂ ,
That is, a signal proportional to the current supplied by converter 15 to the load is detected.

FIG. 5 is a detailed block diagram of the digital pulse width controller 16 shown in FIG. In FIG. 5, the digital pulse width controller 16 includes an AD converter 1, a microprocessor 2, a rate generator 3, a one shot 4, a trigger 5, an oscillator 6, a JK flip-flop 7, an output buffer 8, an input buffer 9a, and 9b, gate circuits 10a, 10b, 10c, 10d and 10e
It consists of

The input buffer 9a becomes active by the first CS signal 111 sent out by the microprocessor 2, inputs the control signal 110, and outputs the control signal 110 to _D0 in accordance with the RD signal 114 sent out by the microprocessor 2. as data bus 1
Send on 05a. In addition, the input buffer 9b is a third CS signal 1 sent out by the microprocessor 2.
Voltage control data becomes active by 13.
V _D and average current data I _A to data bus 10
1a and sends them out to the data bus 105c in accordance with the RD signal 114 as well.

The AD converter 1 is activated by the second CS signal 112 sent by the microprocessor 2, inputs the voltage V ₂ mentioned above, performs AD conversion, and outputs the data as output current data I ₁ according to the RD signal 114. - Send to bus 105b.

Microprocessor 2 processes data. bus 106
and 107, the above control signal D ₀ , output current data I ₁ , voltage control data V _D and average current data I _A are input, and period data D ₁ and switching pulses are input to set the switching period of the converter unit 15. Pulse width data that controls the pulse width of
Sampling control data D ₃ is sent that sets the sampling timing for detecting D ₂ and output current I ₁ to the center of the above pulse width. Note that pulse width data D ₂ is average current data I _A and output current data
Voltage control data V _D so that the difference from I ₁ is “0”
It is calculated by correcting. Further, the sampling control data _D3 is set to 1/2 of the pulse width control data _D2 described above, and is set so that the output current value is sampled at the center of the output current pulse.

Furthermore, the microprocessor 2 sends out an RST signal 120 that generates switching pulses for the converter 15 and an SP signal 121 that instructs sampling of the output current data _I1 .

The rate generator 3 is activated by the fifth CS signal 116 sent out by the microprocessor 2, and inputs periodic data _D1 in accordance with the WR signal 119 also sent out by the microprocessor 2. Then, the oscillator 6 starts counting the CLK signal 122 sent out in accordance with the RST signal 120, and sends out the OUT1 signal 123 every time the count becomes equal to the period data _D1 .

The one shot 4 is activated by the sixth CS signal 117 sent by the microprocessor 2, and outputs pulse width data D ₂ according to the WR signal 119.
Enter. Then, it starts counting the CLK signal 122 in accordance with the above-mentioned OUT1 signal 123, and sends out the OUT2 signal 124 with a pulse width such that the count number is equal to the pulse width data _D2 .

Trigger 5 is activated by the seventh CS signal 118 sent by microprocessor 2,
Sampling control data according to WR signal 119
Enter D ₃ . Then, the OUT2 signal 124 is inverted by the gate circuit 10a.
Start counting the CLK signal 122 according to 8,
The OUT3 signal 125 is sent out every time the count number becomes equal to the sampling control data _D3 .

JK flip-flop 7 is OUT1 signal 123
Q signal 126 and signal 127 whose phases differ from each other by half a period are sent out each time the signal is input.

Gate circuits 10c and 10d receive Q signal 12
6, 127 and 2 signals 128 respectively.

The gate circuit 10b receives the OUT3 signal 125 and outputs its inverted signal 3 signal 129.
Further, the gate circuit 10e sends out an INT signal 130 in accordance with the SP signal 121 and the 3 signal 129, and the microprocessor 2 receives the output current data.
Instructs an interrupt to sample I ₁ .

The output buffer 8 is activated by the fourth CS signal 115 sent by the microprocessor 2, receives the output current data _I1 in accordance with the WR signal 119, and also inputs the output current data I1 in the control signal 110.
data bus 108 respectively according to the DIRC signal.
Send to.

Next, the operation of the parallel operation power supply device 20 configured as described above will be explained.

6a and 6b are the master module 20a in the parallel operation power supply device 20 shown in FIG. 1, respectively.
3 is a waveform diagram illustrating data transfer between and slave modules 21, 22, and 23. FIG. 6th
Figure a illustrates data transfer from a slave module to a master module. In the figure, when the DIRC signal is at a low level, the master module sends an address #n (n=1 to 3) for identifying the slave module in accordance with the STRB signal and the ATN signal. Next, DIRC
When the signal becomes high level, the output current data In(n
= 1 to 3). Also, Figure 6b shows the master
3 illustrates data transfer from a module to a slave module; In the figure, when the DIRC signal is low level, the master module is STRB
Send voltage control data V _D and average current data I _A to all slave modules according to the signal. Note that at this time, the ATN signal is set to high level to instruct the transfer of the voltage control data V _D and average current data I _A described above.

FIG. 7 is a waveform diagram showing the operation of the main parts of the parallel operation power supply device 20. In the same figure, for synchronous T ₀
The CLK signal 122 is the basis for the operation of the slave module 21 of the parallel power supply 20.

First, the rate generator 3 inputs periodic data D ₁ (=n ₃₀ ) according to the WR signal 106, and then inputs the CLK signal 122 according to the RST signal 120.
Start counting. In the same figure, n ₃₀ = 10,
When the above count becomes equal to this,
The OUT1 signal 123 is being sent.

Also, according to the WR signal 119, one shot 4
input the pulse width data D ₂ (n ₄₀・n ₄₁・n ₄₂ ),
Next, CLK signal 1 according to OUT1 signal 123
Start counting 22. In the figure, n ₄₀ = 2, and the OUT2 signal 124 is kept at a low level for the time until the above count becomes equal to this (the cases where n ₄₁ = 4 and n ₄₂ = 6 are also shown in the same way). Furthermore, since the Q signal 126 and signal 127 sent out by the JK flip-flop 7 in accordance with the OUT1 signal 123 are repeatedly inverted as shown in the figure,
The control pulses A1 and A2 follow the period of the OUT1 signal 123 and the pulse width of the OUT2 signal 124, and are pulse signals whose phases differ by a half period. Then, the voltage V 1 generated in the pulse transformer T ₁ of the converter section 15 controlled by the control pulses A 1 and A ₂ and the current transformer
The current I _R flowing to the secondary side of T2 also changes as shown in the figure.

Furthermore, the trigger 5 inputs the sampling control data D ₃ = (n ₅₀ · n ₅₁ · n ₅₂ ) according to the WR signal 119, and then starts counting the CLK signal 122 according to the GATE signal 128 (2 signals). do.
In the figure, n ₅₀ = 1, and when the above count becomes equal to this, the OUT3 signal 125 is sent out (the cases where n ₅₁ and n ₅₂ = 3 are also shown in the same way). If the SP signal 121 is at a high level when sending out the signal 125, the gate circuit 10e sends out the INT signal 130 and samples the above-mentioned current I _R. This current I _R corresponds to the output current data I ₁ converted and output by the AD converter 1 in FIG. 5. In this manner, output current data is sampled at the center of the output current pulse and fed back to master module 20a.

Note that the above operation is exactly the same even if there are a plurality of slave modules. That is, one master module can easily control a plurality of slave modules with good current balance.

〔Effect of the invention〕

The parallel operation power supply device of the present invention has the advantage that by processing various control data as digital data, it is possible to accurately balance currents, which has been difficult with conventional methods. That is, the average value of the output current of each slave module is calculated, and the output current of each slave module can be easily controlled to be equal to the above average value.

In addition, the parallel operation power supply device of the present invention can detect overcurrent by comparing each of the above output current values with a standard value, and further detects that the value is "0". It also becomes possible to check for failures. In other words, there is an advantage that a circuit consisting of individual parts is not particularly required to realize these functions.

Furthermore, by employing the digital circuit as described above, the parallel operation power supply device of the present invention has the advantage that it is less likely to be disturbed by noise and can improve controllability.

[Brief explanation of drawings]

FIG. 1 is a block diagram including an embodiment of the parallel operation power supply device according to the present invention, FIG. 2 is a detailed block diagram of the master module shown in FIG. 1, and FIG. 3 is a detailed block diagram of the slave module shown in FIG. 1. 4 is a detailed block diagram of the converter section shown in FIG. 3, FIG. 5 is a detailed block diagram of the digital pulse width control section shown in FIG. 3, and FIGS. A waveform diagram for explaining data transfer from the module to the master module and data transfer from the master module to the slave module. FIG. 7 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1. be. 1, 11...AD converter, 2, 12...Micro processor, 3...Rate generator, 4...One shot, 5...Trigger, 7...
JK flip flop, 10a, 10b, 10
c, 10d, 10e...gate circuit, 20a...
Master module, 21, 22, 23...slave module.

Claims (1)

[Claims] 1. Each of a plurality of DC stabilized power supply devices having a switching circuit is a slave module,
In the parallel operation power supply device having a master module that connects the plurality of slave modules in parallel and controls each of them, the master module inputs the output voltage of the parallel operation power supply device and receives a digital signal of the output voltage.・The first to send data
An AD converter inputs the digital data of the output voltage and sends out the difference between the digital data corresponding to a preset reference voltage and the digital data of the output voltage as voltage control data to the slave module. a first microprocessor that inputs output current data from each of the slave modules and sends out an arithmetic average value thereof as average current data, and sends out a control signal for controlling data transmission and reception with each of the slave modules; and each of the slave modules includes a second AD converter that inputs a voltage proportional to the output current of the slave module and sends out digital data of the voltage as the output current data; The voltage control data and the average current data are input, and the voltage control data is corrected so that the difference between the output current data and the average current data is "0", and the pulse width data and the switching period of the switching circuit are determined. period data to be set, sampling control data having a size half of the pulse width data in order to sample the output current data at the center of the ON time of the switching pulse of the switching circuit, the pulse width data and the period. for generating the switching pulse from the data.
a second microprocessor that sends an RST signal and an SP signal that instructs sampling of the output current data; and an OUT1 signal that inputs the periodic data and starts a switching operation of the switching circuit according to the RST signal. and a programmable one shot that inputs the pulse width data and sends out an OUT2 signal in accordance with the OUT1 signal to set the switching pulse width of the switching circuit to a magnitude indicated by the pulse width data. and inputting the sampling control data and setting the sampling timing of the output current data.
The OUT3 signal is combined with the sampling control data.
A programmable trigger that sends out according to the OUT2 signal, and a JK that inputs the OUT1 signal and sends out the Q signal and the signal as a two-part signal of the OUT1 signal.
inputting the flip-flop, the OUT2 signal, the OUT3 signal, the Q signal, and the signals, and transmitting a signal for setting the switching operation of the switching circuit, and transmitting the signal to the second microprocessor according to the SP signal; Instruct to import output current data
1. A parallel operation power supply device comprising: an INT signal; and a gate circuit that sends out an INT signal.