JPH0446216Y2 - - Google Patents

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Publication number
JPH0446216Y2
JPH0446216Y2 JP10322486U JP10322486U JPH0446216Y2 JP H0446216 Y2 JPH0446216 Y2 JP H0446216Y2 JP 10322486 U JP10322486 U JP 10322486U JP 10322486 U JP10322486 U JP 10322486U JP H0446216 Y2 JPH0446216 Y2 JP H0446216Y2
Authority
JP
Japan
Prior art keywords
trigger
signal
memory
input signal
displayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10322486U
Other languages
Japanese (ja)
Other versions
JPS6310463U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10322486U priority Critical patent/JPH0446216Y2/ja
Publication of JPS6310463U publication Critical patent/JPS6310463U/ja
Application granted granted Critical
Publication of JPH0446216Y2 publication Critical patent/JPH0446216Y2/ja
Expired legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Details Of Television Scanning (AREA)

Description

【考案の詳細な説明】 〔技術分野〕 本考案は例えばデイジタル・ストレージ・オシ
ロスコープ等の波形記憶装置における波形記憶回
路の改良に関するものである。
[Detailed Description of the Invention] [Technical Field] The present invention relates to an improvement of a waveform storage circuit in a waveform storage device such as a digital storage oscilloscope.

〔従来技術とその問題点〕[Prior art and its problems]

従来の波形記憶装置では、入力信号を常時A/
D変換し、このデイジタル化した入力信号のメモ
リへの書込みはトリガがかかつた後所定の量を無
条件で行なつていた。この間にトリガがかかつて
も無視していた。観測の対象が正常に動作してい
る場合はこの方式で良い。しかし、入力信号に異
常が発生した場合、この時の波形を観測、解析す
る必要があるが、トリガがかからなくなる事が多
く、従つて従来の波形記憶装置では観測が極めて
困難であつた。
In conventional waveform storage devices, the input signal is always A/
A predetermined amount of the D-converted and digitized input signal is unconditionally written into the memory after a trigger is applied. During this time, a trigger occurred, but I ignored it. This method is fine if the observation target is operating normally. However, when an abnormality occurs in the input signal, it is necessary to observe and analyze the waveform at this time, but the trigger often fails, and therefore observation is extremely difficult with conventional waveform storage devices.

〔目的〕〔the purpose〕

本考案は、入力信号のレベルが正常な時は無視
し、異常があつた場合のみにこれを記憶、表示す
る事を特徴とし、その目的は異常現象を確実に捕
らえての観測、解析を容易ならしめる事にある。
This invention is characterized by ignoring the input signal level when it is normal, and storing and displaying it only when an abnormality occurs.The purpose of this invention is to easily capture abnormal phenomena and facilitate observation and analysis. It's about getting used to it.

〔実施例〕〔Example〕

本考案は、異常発生時の波形を観測する為に
は、直前のトリガ点からの入力信号をAD変換、
記憶すれば良いという点に着目し成されたもので
ある。つまり、トリガのかかる間隔をΔtとする
時、Δt内にトリガがかかつた時は最初から記憶
をやり直し、トリガがかからなかつた場合のみ表
示するようにしたものである。
In this invention, in order to observe the waveform when an abnormality occurs, the input signal from the previous trigger point is converted into an AD signal.
It was created with the focus on the point that all you have to do is memorize it. In other words, when the interval between triggers is Δt, if a trigger occurs within Δt, the memory is rewritten from the beginning, and only when the trigger does not occur, it is displayed.

以下本考案の一実施例を図により説明する。実
施例は1:入力信号、2:アツテネータ、3:
AD変換回路、4:トリガ信号発生回路、5:カ
ウンタ、6:AD変換終了を示す信号、7:カウ
ント値の対応したアドレス信号、8:1画面分の
データ数までカウントした事を示す信号、9,1
1:メモリ、10:データ転送回路、12:表示
制御回路、13:ブラウン管、14:11が全デ
ータ転送を終了した事を示す信号より構成され
る。
An embodiment of the present invention will be described below with reference to the drawings. Examples are 1: input signal, 2: attenuator, 3:
AD conversion circuit, 4: trigger signal generation circuit, 5: counter, 6: signal indicating the end of AD conversion, 7: address signal corresponding to the count value, 8: signal indicating that the number of data for one screen has been counted, 9,1
1: memory, 10: data transfer circuit, 12: display control circuit, 13: cathode ray tube, 14: 11 is a signal indicating that all data transfer has been completed.

次にこの動作を説明する。入力信号1はアツテ
ネータ2により適切なレンジに収められた後、
AD変換回路3、トリガ信号発生回路4に入力さ
れる。AD変換回路3は所定の間隔でAD変換を
行ない、結果をメモリ9に書込む。アドレスはア
ドレス信号7により決められる。トリガ信号発生
回路4は入力レベルを判断してトリガがかかつた
事を示す信号をカウンタ5へ出力する。カウンタ
5はAD変換終了を示す信号6をカウントし、ア
ドレス信号7を出力するが、トリガがかかるとリ
セツトされ、再度初期値からカウントを始める。
この様にしてメモリ9には常に最後にトリガがか
かつた時点以降のデータが書込まれる。従つて、
1画面分のAD変換が終了する前にトリガがかか
つている状態、つまり正常状態ではメモリ9は1
画面分のデータを記憶する前に常に書替えられて
いる。そして、トリガがかからなくなると1画面
分の回数のAD変換が終了し、カウンタは信号8
を出力する。メモリ9の信号8がONとなると、
以後OFFとなる迄書込みは行なわない。データ
転送回路10は信号8がONとなるメモリ9の内
容をメモリ11へ転送し、これを終ると終了信号
14を出力する。カウンタ5は終了信号14が
ONとなるとカウンタ5をリセツト、信号8を
OFFとし、再度AD変換結果のカウント、書込み
を始める。表示制御回路12はメモリ11の内容
を読出し、ブラウン管13へ表示する。この様に
して最後にかかつたトリガ以降の波形のみをブラ
ウン管13へ表示する。
Next, this operation will be explained. After input signal 1 is brought into an appropriate range by attenuator 2,
The signal is input to the AD conversion circuit 3 and the trigger signal generation circuit 4. The AD conversion circuit 3 performs AD conversion at predetermined intervals and writes the results into the memory 9. The address is determined by address signal 7. Trigger signal generation circuit 4 determines the input level and outputs a signal indicating that a trigger has been applied to counter 5. The counter 5 counts the signal 6 indicating the end of AD conversion and outputs the address signal 7, but when a trigger is applied, it is reset and starts counting again from the initial value.
In this way, data from the time when the last trigger is applied is always written into the memory 9. Therefore,
In the state where the trigger is applied before AD conversion for one screen is completed, that is, in the normal state, memory 9 is 1.
The screen's worth of data is always rewritten before it is stored. Then, when the trigger is no longer applied, the AD conversion for one screen is completed, and the counter receives the signal 8.
Output. When signal 8 of memory 9 turns ON,
From then on, no writing will be performed until it is turned OFF. The data transfer circuit 10 transfers the contents of the memory 9 when the signal 8 is turned on to the memory 11, and outputs the end signal 14 when this is completed. The counter 5 receives the end signal 14.
When it turns ON, counter 5 is reset and signal 8 is turned on.
Turn it OFF and start counting and writing AD conversion results again. The display control circuit 12 reads out the contents of the memory 11 and displays them on the cathode ray tube 13. In this way, only the waveforms after the last trigger are displayed on the cathode ray tube 13.

つまり、入力信号1が正常であればトリガ以後
のデータはメモリ9に記憶されるが、次のトリガ
により入力したデータでこのメモリ9の内容は書
き替えられる。入力信号1が正常であればこの動
作を繰り返すため、ブラウン管13上には波形は
表示されない。入力信号1の異状(トリガがかか
らなくなるような異状)があつた場合は、最後に
かかつたトリガ以後のデータがメモリ9に記憶さ
れて行くがこの間トリガはかからないため、メモ
リ9はフル状態になる。メモリ9がフル状態にな
れば前述のように、入力データは表示制御回路1
2等を経由し、ブラウン管13に表示される。
That is, if the input signal 1 is normal, data after the trigger is stored in the memory 9, but the contents of the memory 9 are rewritten with data input by the next trigger. If the input signal 1 is normal, this operation is repeated, so no waveform is displayed on the cathode ray tube 13. If there is an abnormality in the input signal 1 (an abnormality that causes the trigger to no longer be applied), the data after the last trigger will be stored in the memory 9, but since no trigger will be applied during this time, the memory 9 will be in a full state. become. When the memory 9 becomes full, the input data is transferred to the display control circuit 1 as described above.
It is displayed on the cathode ray tube 13 via the second etc.

従来の波形記憶装置においては1画面内に複数
個のピークが表示される様に、AD変換の間隔を
選ぶのが普通であり、この場合複数回トリガがか
かる。
In conventional waveform storage devices, the AD conversion interval is usually selected so that multiple peaks are displayed within one screen, and in this case, the trigger is applied multiple times.

本実施例においても同様にすれば、異常発生時
の波形を確実に記憶、表示する事ができる。
In this embodiment as well, by doing the same, the waveform when an abnormality occurs can be reliably stored and displayed.

〔効果〕〔effect〕

以上本考案により、信号レベルの低下を伴なう
異常発生を確実にとらえ、表示する事ができる。
従つてこの様な異常現象、特にこれが希にしか発
生しない場合の解析に有効である。また無人運転
を要求されるシステムの異常検知、解析に有効で
ある。
As described above, according to the present invention, it is possible to reliably detect and display the occurrence of an abnormality accompanied by a decrease in the signal level.
Therefore, it is effective in analyzing such abnormal phenomena, especially when they occur only rarely. It is also effective in detecting and analyzing abnormalities in systems that require unmanned operation.

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の実施例のブロツク図で、その主要
部分は2……アツテネータ、3……AD変換回
路、4……トリガ信号発生回路、5……カウン
タ、9,11……メモリ、12……表示制御回
路、13……ブラウン管である。
The figure is a block diagram of an embodiment of the present invention, and its main parts are 2...attenuator, 3...AD conversion circuit, 4...trigger signal generation circuit, 5...counter, 9, 11...memory, 12... . . . Display control circuit, 13 . . . Braun tube.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号がトリガ発生回路からのトリガ信号の
タイミングで入力し、アツテネータにて適切なレ
ンジに収められた入力信号をAD変換し、この
AD変換回数をカウントし、前記AD変換された
結果をメモリ内の、変換回数に応じたアドレスへ
書込み、所定量に達すると書込みをやめて転送回
路にて表示用メモリへ転送し、この内容を表示制
御回路にてブラウン管へ表示する波形記憶装置で
トリガがかかる都度トリガ発生回路がカウンタを
リセツトする事により、カウンタの値が所定の値
に達する迄トリガがかからなかつた場合のみ波形
を記憶、表示することを特徴とする波形記憶装
置。
The input signal is input at the timing of the trigger signal from the trigger generation circuit, and the attenuator converts the input signal within an appropriate range.
Counts the number of AD conversions, writes the AD converted results to the address in memory according to the number of conversions, and when a predetermined amount is reached, stops writing, transfers the data to the display memory using the transfer circuit, and displays this content. Each time a trigger is applied to the waveform storage device that is displayed on the cathode ray tube in the control circuit, the trigger generation circuit resets the counter, so the waveform is stored and displayed only if no trigger is applied until the counter value reaches a predetermined value. A waveform storage device characterized by:
JP10322486U 1986-07-07 1986-07-07 Expired JPH0446216Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10322486U JPH0446216Y2 (en) 1986-07-07 1986-07-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10322486U JPH0446216Y2 (en) 1986-07-07 1986-07-07

Publications (2)

Publication Number Publication Date
JPS6310463U JPS6310463U (en) 1988-01-23
JPH0446216Y2 true JPH0446216Y2 (en) 1992-10-29

Family

ID=30975580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10322486U Expired JPH0446216Y2 (en) 1986-07-07 1986-07-07

Country Status (1)

Country Link
JP (1) JPH0446216Y2 (en)

Also Published As

Publication number Publication date
JPS6310463U (en) 1988-01-23

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