JPH0446432A - Atm cell flow restriction system - Google Patents

Abstract

PURPOSE:To restrict cell flow and to simplify the circuit by subtracting a value resulting from a quotient multiplied with a time (from a point of time of preceding subtraction till arrival of the cell) from a count of a cell counter memory and comparing the difference with a specific value. CONSTITUTION:A periodic subtraction circuit 2 is executed in the unit of a specific time and subtracts a 1st specific value from a count stored in a cell counter memory 1. Then at calling, the 1st specific value through a cell flow restriction control circuit 3 and used for the subtraction of the periodic subtraction circuit 2 is divided by specific time and the quotient is multiplied with a time from a point of time of preceding subtraction till arrival of a cell is subtracted from the count of the cell counter memory 1, and the difference is compared with a 2nd specific value and whether or not the cell is aborted is discriminated depending on the result of comparison. For example, when the result is discriminated to be larger than the 2nd specific value, the cell is aborted and when the result is discriminated to be smaller than the 2nd specific value, the cell is allowed for the entry in the network.

Description

[Detailed Description of the Invention] [Summary] Regarding an ATM cell inflow regulation method that regulates the inflow of input cells, an ATV that efficiently performs a cell inflow regulation circuit with a small-scale circuit is provided.
In an ATM network that aims to provide a cell inflow control method, it calculates the bandwidth based on the bandwidth that the subscriber applies for when making a call, and then decides whether to permit or deny the call. a counter memory that stores the number of cells; a periodic subtraction circuit that subtracts a first specific value greater than 1 from the counter value stored in the cell counter memory in units of a specific time; and a counter value stored in the cell counter memory. A cell inflow regulation control circuit is configured to determine whether or not to discard a cell when the cell arrives.

[Industrial application field]

The present invention relates to an ATMM 4, and more particularly to an ATV cell inflow regulation method for regulating the inflow of input cells.

[Traditional techniques]

Currently, as the amount of data increases, there is a demand for faster communication networks. ATMs are being considered to cope with this increase in speed.

In an ATM network, a subscriber applies to the network for a bandwidth when making a call, and the network calculates the bandwidth based on that value and decides whether to permit or reject the call. However, if the amount of cells flowing into the network is extremely different from the declared value due to malicious intent on the part of the subscriber or unforeseen circumstances, the prerequisites for calculating the bandwidth at the time of calling will be broken, and the Cell discards occur frequently and can have a significant impact on other calls.

For this reason, the inflow of cells into the network is monitored at the network entrance (subscriber interface), and if the inflowing cells from the subscriber are extremely different from the applied value, the cells flowing in beyond the declared value are discarded. There is.

FIG. 9 is a block diagram of the subscriber exchange. Subscriber exchange 1
0 consists of a subscriber handling section 13 consisting of a subscriber line termination device 11 and a cell inflow regulating section 12, and a switching section (SW) 14. Transfer requests, etc. added from the subscriber line are sent to the subscriber vAP.
, joins the end device 11 and applies a cell transfer request to the cell inflow regulating section 12. Then, the cell inflow regulating section 12 monitors the input to the network entrance, that is, the switching section 14 described above, and if the cells input from the subscriber are extremely different from the applied value, it discards the cells that flow in beyond the declared value. ing. Note that if the amount of cells does not exceed the declared amount, the cells are sent to the exchange section 14.

The cell inflow regulating section 12 in FIG. 9 conventionally uses a leaky bucket system.

In this method, a counter is provided that counts up by ``°1'' when a cell comes in, and decrements by ``1'' at regular intervals, and when the value of the counter exceeds a certain value, the cell is Discard. That is, FA(t)=G(t)-18T
(t/T)... Find equation (1) and FA(t)<
If α, enter the cell into the network; if FA(t)>α, discard the cell. Here, FA(L) is the counter value,
INT (X) is a function that rounds down the decimal places, G(t
) is the number of incoming cells at time t, T is the subtraction period (S), α
is the allowable value (number of cells).

On the other hand, as a characteristic of ATM networks, multiple calls exist on one interface. In consideration of this point, in the past, the subscriber interface section was made smaller and the processing of Leekino\Kent was multiplexed.

FIG. 1O is a block diagram of a conventional system. The circuit shown in FIG. 10 implements the leaky bucket system of the cell inflow regulating section 12 shown in FIG. 9. This circuit includes a cell inflow regulation control circuit 15, a cycle subtraction circuit 16, a timer 18, a memory access contention arbitration section 19, a delay circuit 20, a cell counter memory 21, an empty cell pattern generator 22, a selector 23,
It consists of a CPU interface 24. Cells flowing in from the transmission path ink face, that is, subscriber line termination equipment, are temporarily stored in the delay circuit 20, and the VC in the cell's terminal is
The cell inflow regulation control circuit 15 identifies the call from I, reads the count value from the cell counter memory 21 at the memory address where the cell counter value of the corresponding cell is stored, and determines that the cell count value does not exceed a certain value. determine whether
If it exceeds the limit, the cell is discarded. Then, add 1 to the cell counter value and write it into the memory.

In addition, the period subtraction circuit 16 reads out all memory addresses in response to the clock applied by the timer 18 at a fixed time, calculates each by 1:$i (-1), and writes the result to the rotated memory address. When the aforementioned cell inflow regulation control circuit 15 determines that the value does not exceed a certain value, the selector 23 selects the cell temporarily stored in the delay circuit 20 and outputs it to 5W14.

If it exceeds the limit, the selector 23 selects an empty cell pattern generated by the empty cell pattern generator 22 and outputs it to 5W14 in order to discard the cell.

The selection of the selector 23 is controlled by the cell inflow regulation control circuit 15 described above. Through the above-described operations, a bandwidth calculation is performed based on the usage band requested at the time of a call, and it is determined whether or not to permit the call, that is, whether or not to send a cell. FIG. 11 is a block diagram of a conventional cell counter memory. Cell counter memories 21 are provided corresponding to respective areas of each VCI.

The memory access contention arbitration unit 19 responds to the access request from the CPU with the cell counter memory 21 and the period subtraction circuit 1.
6 access. When the periodic subtraction circuit 16 outputs an address in response to a periodic subtraction request from the timer 18, the memory access conflict arbitration unit 19 outputs the address to the cell counter memory 21, and the data output from the cell counter memory 21 is periodically It is output to the subtraction circuit 16. Then, the value reduced by 1 is stored in the cell counter memory 21 again. The same applies to the call to the cell counter memory 21 from the cell inflow restriction control circuit 15 described above.

FIG. 12 is a processing flowchart of a conventional cell inflow regulating circuit. The cell inflow regulating circuit 15 determines whether or not a cell has arrived (Sl)L, and repeats this determination (Sl) if no cell has arrived. When cells are arriving (YES
) contains cell counter memory 2 corresponding to the arrived cell.
1 and loads the VCI count value of that cell (S2). Next, it is determined whether the cell counter value is greater than or equal to a specific value (α) (33) L, and if it is greater than or equal to α (YES
), the cell is discarded (S4) L, and the determination is repeated from step S1. Also, in the determination (S3), the cell counter value is a specific value (
When it is not more than α) (NO), the cell is passed, so the selector 23 selects the cell stored in the delay circuit 22 5W1
4 (S5).

Next, the cell counter value is +IL (S6), and the counter value is determined as the VCI (S7) again (Sl).
Repeat more.

FIG. 13 is a processing flowchart of the conventional period subtraction circuit 16. The period subtraction circuit 16 uses timer 1 in specific time units.
Execution is started by the timer expiry pulse applied from 8. First, A=1 (S8), and the cell counter value α(A) is loaded from address A (S9). Then, set the cell counter value to -IL (310), check if it is the final address (5ll), and if it is not the final address (NO
), increase A by +1 512) and execute the process again from step S9. When it is determined in the determination (Sll) that the address is the final address (YES), processing for the request from the timer is terminated.

(Problems to be Solved by the Invention) In the conventional method described above, (a) all memory addresses are read and subtracted at fixed time intervals, so when there are many simultaneous calls (currently up to 64 degree) memory addresses increase and periodic subtraction is limited by memory access time.

Furthermore, (b) to prevent this, the memory must be physically divided, which increases the scale of the circuit. (c)A
In the TM network, communication up to several hundred Mbps is carried out in one network, so the subtraction cycle also needs to be made variable depending on the call, but conventional methods have problems such as not being able to handle this process. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide an ATM cell inflow regulation system that efficiently performs a cell inflow regulation circuit using a small-scale circuit.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The present invention is an AT that calculates the bandwidth based on the bandwidth that the subscriber applies for when making a call, and decides whether or not to permit the call.
This is in M4M.

Cell counter memory 1 stores the number of cells.

The period subtraction circuit 2 is executed in specific time units, and subtracts a first specific value larger than the count value from the count value stored in the cell counter memory 1.

The cell inflow regulating circuit 3 determines whether or not to discard a cell when the cell arrives based on the count value stored in the cell counter memory 1. For example, this cell inflow regulation circuit 3 is
The first specific value to be subtracted by the period subtraction circuit 2 is divided by a specific time unit, and the value obtained by multiplying the time from the time of previous subtraction to the time when the cell arrives is subtracted from the count value of the cell counter memory 1. The result is compared with the second specific value, and it is determined whether or not to discard the cell based on the comparison result.

The cell subtraction memory 4 stores the first specific value for each VCI.

[For production]

The period subtraction circuit 2 is executed in specific time units, and subtracts the first specific value from the count value stored in the cell counter memory l. Then, when a call is made, the cell inflow regulation control circuit 3 executes the process, divides the first specific value subtracted by the period subtraction circuit 2 by the specific time, and further calculates the time from the previous subtraction time to the time the cell arrives. The result of subtracting the multiplied value from the counter value of the cell counter memory 1 is compared with the second specific value, and it is determined whether or not to discard the cell based on the comparison result. For example, if the cell is judged to be large in comparison, it is discarded, and if it is judged to be small, the cell is allowed to flow into the network.

The usage band that the subscriber applies for when making a call differs for each subscriber, and is stored in the cell subtraction memory 4 for each VCI of the input call, and the period subtraction circuit 2 subtracts this value in accordance with these. do.

By the above operation, the timer time can be extended,
Compared to the conventional method, only one execution is required for multiple timer interrupts, reducing processing time and increasing the speed of all processing. Furthermore, since the number of subtractions can be changed in units of cells, each can be controlled in accordance with the bandwidth request, and discard can be accurately determined without depending on the bandwidth.

C implementation example The present invention will be described in detail below using the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. In addition, the first
Circuits that are the same as those in the conventional circuit shown in FIG.

The input ATMHW from the subscriber terminal device is added to the cell inflow regulation control circuit 31.
determines whether or not to output the cell stored in the delay circuit 20 to the 5W 14 as the output ATMHW based on the value of the input ATMHW in a counter memory, which will be described later. That is, the cell inflow regulation control circuit 31 selects the output of the empty cell pattern generator 22 when the input ATMHW is instructed to be discarded, and sends a selection control signal to the selector 23 to select the cell of the delay circuit 20 when the input ATMHW is not discarded. Output.

The cell inflow regulation control circuit 31, period subtraction circuit 33, cell counter memory 34, cell subtraction memory 35, and CPU interface 36 are connected by address lines. In addition, the cell inflow regulation control circuit 31, the period subtraction circuit 33, the CPU
The interface 36 and cell counter memory 34 are connected by a counter line. Furthermore, a cell inflow regulation control circuit 31, a period subtraction circuit 32, and a CPU interface 36
, and the cell subtraction memory 35 are connected by a cell subtraction line. The timer 32 is connected to the cell inflow regulation control circuit 131, the period subtraction circuit 33, and the CPU interface 36.

Although not shown, the CP tJ interface 36 is
Connected to U. The conventional period subtraction circuit 16 subtracts one value every T time from the cell counter value stored in the cell counter memory 34, but the period subtraction circuit 32 of the present invention subtracts one value every TI (TI=HXT) time. niN
-) Perform K calculation.

In the above-mentioned subtraction method, is there a per unit time system compared to the conventional example? Bm It looks like there are a lot of people.

In order to correct this, the following means are used to solve this problem. When a cell arrives, the cell inflow control circuit 3J of the embodiment transfers Nx from the cell inflow stored in the memory directly.
(t/TI) is subtracted and this corrected value is used when determining whether to discard or pass the cell. Note that T1 is the elapsed time from the time of the previous subtraction to the time of arrival of the cell.

That is, FB(t)=G(t)-NxW(t/TI)...
・-(2) 2FIB(t)-F(t)-N XW(tl
/TI) --- (3) If FAI(t)<α, the cell is added to the network, and if FAI(t)>α, the cell is discarded.

In addition, FA(t) is the counter value, β is the tolerance value (number of cells)
, W(t) is a function that cuts off the bottom of the decimal point board, G(t)
is the number of incoming cells in time, T1 is the subtraction period of the cell counter memory (TI=NXT: T is the conventional cell subtraction period),
β is an allowable value (number of cells).

The period subtraction circuit 32 described above subtracts by N every time T1, but this may be fixed or may be variable for each terminal or call.

If it is variable, it is stored in the cell subtraction memory 35 in VC1 units of cells, and the period subtraction circuit 32 generates an address corresponding to ■CI units, reads data from the cell counter memory 34, and stores the data in the corresponding cell subtraction memory 35. It also reads out the contents of , subtracts the number of cells to be subtracted from the counter value, and outputs the result to the cell counter memory 34. Memory has period T1
The number of cells to be subtracted for each MCI is stored. The period subtraction circuit 32 subtracts the number of cells stored in the subtraction memory from the counter value stored in the cell counter memory for each period Tl and for each MCI. In addition, the number of cells N1 to be stored in the subtraction memory and the subtraction period T2 are N1=NxW (2/T) --------- (4)
have the relationship of Eq.

For example, if you want to make the subtraction period 1/2 of the basic subtraction period T, store 2XN in the subtraction memory and TI (TI=
Subtract 2N for every N XT). By doing this, the same effect as adding one cell every T/2 period can be obtained.

FIG. 3 is a block diagram of the cell counter memory, and FIG. 4 is a block diagram of the subtraction cell number memory. The cell counter memory 34 and the cell subtraction memory 35 store the cell counter A and the number of cells to be subtracted B by associating addresses for each MCI, and the period subtraction circuit 32 outputs the same address to the address line to store the cell counter The values in the memory 34 and the cell subtraction memory 35 are called. Then, the values stored in the cell counter memory and the subtraction cell number memory are subtracted in specific time units added from the timer 32. Furthermore, the result is stored in the cell counter memory 34.

Note that although the memories in FIGS. 3 and 4 have four VCIs, the number is not limited to this. Furthermore, since the MCI is regulated every time a call is made, the CPU stores the number of subtracted cells in the cell subtraction memory 35 via the cell inflow regulation control circuit 31 and the CPU interface 36 in accordance with this value.

FIG. 5 is a diagram showing the structure of an ATM header of a cell. One cell consists of 8-bit octets 1 to 53, with Busy, REQ, and VPI fields in octet 1 and VPI field and VPI/VCI in octet 2.
field, VCI field in octet 3, same < ver field in octet 4, PR, PT,
HEC is provided in octet 5, and octets 1 to 5 constitute an ATM header.

On the other hand, when a cell arrives, the cell inflow control circuit 31 calculates N from the cell counter value stored in the cell counter memory.
2xlNT (t 1/TI) is subtracted, and based on this corrected value, it is determined whether the cell should be discarded or passed. Note that here, tl is the elapsed time from the time of the previous subtraction to the time of arrival of the cell.

That is, FC(t)=G(t)−N2X INT(t/TI)・
...(5) 2 PCI (t)=FA (t) -
N2 do.

Here, β is the allowable value (number of cells), and N2 is the subtraction cell stored in the subtraction memory.

In order to further explain the present invention, the following preconditions will be set and explained.

(2) To simplify the explanation, it is assumed that VCI has only numbers 0 to 3. (Actually, from 0 to 64) ① The basic period of the cell subtraction period is the passage time of two cells.

■The subtraction period of the cell counter is the passage time of 4 cells.

(2) The allowable value β is set to 2 as a constant value.

(2) The initial value of the cell counter value when VCI=O is set to 0.

(2) Assume that input cells HW and output cells HW flow at regular intervals (cell period) as shown in FIG.

(2) The timer is synchronized with the input cell MW and is composed of a 12-decimal counter that operates with a clock that is 1/3 of the cell period.

FIG. 8 is an operation timing chart under the above-mentioned preconditions. At time t3 in FIG. 8, a cell (VCI=O) is input from the input ATMHW.

At this time, the cell inflow regulation control circuit 31 reads the control counter value and cell subtraction number corresponding to vc I=o from the address O of the cell counter memory 34 and the cell subtraction memory, respectively (in this case, the cell counter value −〇(
(from preconditions), cell subtraction number - 2 (4) formula and preconditions)
.

FIG. 7 is a processing flowchart of the period subtraction circuit. Due to the above-mentioned preconditions in the embodiment of the present invention, the timer 32
When becomes 3N+1, the cycle subtraction circuit 32 is activated to perform cycle subtraction and start processing. First, E=(t-1)/3
(S20).

That is, the address containing the cell counter value to be subtracted this time is found. Then, the cell counter value A (E) and the cell subtraction value B (E) are loaded (S21).

In this process (S21), the atrus obtained in the process (S22) is stored in the cell counter memory 34 and the cell subtraction memory 35.
The value corresponding to the address is read out using the cell counter line and the cell subtraction number line. Next, the period subtraction circuit 32 calculates the cell counter value A (E) - cell subtraction number B (
E) and stores it in the cell counter memory 34 as A (E) (522). Next, it is determined whether A (E) has become negative, and if it is not negative (No), the process is terminated, and if it is negative, A (E)=O is set and the process is terminated. This process (S23.524) prevents the cell counter value from becoming negative.

Further, the inflow regulation control circuit 32 obtains a correction value from the above-mentioned cell subtraction number and the timer value. In this case, the correction value becomes 0, and the cell inflow restriction control circuit 32 determines that the control can be passed. At this time, the cell regulation cell circuit adds 1 to the cell counter value and writes it to the cell counter, and sets the selector in Figure 2 to 0 to allow this cell to pass (the cell is a delay circuit and the above processing is will be remembered until completed).

FIG. 6 is a processing flowchart of the cell inflow regulation control circuit 32. The cell inflow regulation circuit 3I always operates and determines whether or not a cell has arrived (S31). After making this determination, if it has not arrived (NO), this determination (S31) is repeated again.

If it has arrived (YES), the cell counter value A (N) corresponding to VCT is loaded with the cell subtraction number B (N) (332), and then a correction value is calculated (S33). That is, D=INT(B(N) X (t-3N) mod 12/
12).

Here, L is a timer value.

Next, determine whether A (N)-D+1>β53
4), when it is not more than β (NO), let the cell pass (
S35). That is, the selector 23 is selected to the 0 side, and the cell stored in the delay circuit 20 is outputted to the 5W 14 as an output ATM highway. and A (N) −A (N
)+1 and save 336), A(N) (S37
). Also, in the determination (S34), if it is greater than β (YES
), the cell is discarded (S38). That is, the 1 side of the selector 23 is selected to output the pattern of the empty cell pattern generator 22 as the output ATMHW. Processing (S37.5
After step 38) is completed, the process is repeated from step S31. Through the above operations, the cell inflow regulation control circuit 31 sequentially determines whether the cell is to be discarded or passed each time a cell arrives, and executes processing corresponding to each case.

On the other hand, at time t6 in FIG. 8, the cell (
VCI=O) is input. At this time, the cell counter value=1, the number of subtracted cells=1, the correction value=1, and the value after correction=1. Therefore, the cell inflow restriction control circuit 32 determines that it is okay to let the cells pass. At this time, the cell inflow regulation control circuit 32 adds 1 to the cell counter value and writes it into the cell counter memory 34, and sets the selector 23 to the 0 side to allow this cell to pass.

At time t9 in FIG. 8, from the input ATMHW to the cell (VC
I=O) is input. At this time, cell counter value -2 cell subtraction number = 1 correction value = 1 value after correction = 2. Therefore, in the cell inflow regulation cell output, ver.
It is determined that the cell inflow of =o exceeds the permissible limit. At this time, the cell inflow regulation control section 32 sets the selector 23 to the 1 side and sends out empty cells to the outgoing cell HW.

On the other hand, the cycle subtraction circuit 32 is activated periodically (once per cell) and periodically subtracts the cell counter value corresponding to the stored VCI according to the operation flow shown in FIG. 6 described above. Also,
The cell counter value of ve r =o is subtracted at time t1 and time t9.

To explain the operation using time t=9 as an example, first, the timer 32 issues an activation request to the period subtraction circuit 33, and the period subtraction circuit 33 is activated and performs the following operations.

■Decided to process VCI=O based on the timer value,
From the cell counter memory and cell subtraction memory, VCI=O
The cell counter value, cell counter memory, and cell subtraction number are read out.

■Subtract the number of cells subtracted from the cell counter memory value.

At this time, 2-2=O.

■Determine whether the cell counter is not negative or not, and if it is negative, count all the cells. In this case, since it is 0, no processing is performed.

Although the present invention has been described in detail using the embodiments described above, the present invention is not limited thereto, and a plurality of cell counter memories 34 and cell subtraction memories 35 are provided, and a group unit is used for calls corresponding to individual terminals. It is also possible to set up and manage it. In addition, the number of period subtraction circuits 32 is one, and the delay circuit selector 23 such as the cell inflow regulation control circuit 31 is also one, but the number is not limited to this, and one cell counter memory 34 can be provided by a plurality of circuits.
, cell subtraction memory 35 may be used.

〔Effect of the invention〕

As described above, according to the present invention, the number of memory accesses is reduced, the circuit is simplified, and the cost and consumption of the system are reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, Figure 3 shows The fourth time is Figure 5 shows Figure 6 shows -t, Figure 7 shows Figure 8 shows Figure 9 shows Figure 10 shows Figure 11 shows Figure 12 shows - chart, Figure 13 shows It is. 1... 2... 3... 4... cell inflow regulation circuit, period subtraction circuit, Cell inflow regulation control circuit, Cell subtraction memory. Cell counter memory configuration diagram, Configuration diagram of subtraction cell number memory, Configuration diagram of cell ATM header, Processing flowchart of cell inflow regulation circuit Processing flowchart of the period subtraction circuit, Operation timing chart, Configuration diagram of subscriber exchange, Configuration diagram of conventional method, Configuration diagram of conventional cell counter memory, Processing flow of conventional cell inflow regulation circuit Processing flowchart of period subtraction circuit

Claims (1)

[Claims] 1) In an ATM network that calculates the bandwidth based on the usage bandwidth that a subscriber applies for when making a call and decides whether to permit or reject the call, the number of cells is stored. a period subtraction circuit (2) that subtracts a first specific value greater than 1 from a counter value stored in the cell counter memory (1) in units of specific time; 1.) An ATM cell inflow regulation system comprising: a cell inflow regulation control circuit (3) which determines whether or not to discard a cell when the cell arrives, based on a counter value stored in the counter value stored in the counter value stored in the cell inflow control circuit (3). 2) The cell inflow regulation control circuit (3) divides the first specific value to be subtracted by the period subtraction circuit (2) by the specific time, and further multiplies the time from the time of previous subtraction to the time of arrival of the cell. 2. The ATM cell inflow regulating system according to claim 1, wherein the result of subtracting the value from the counter value is compared with a second specific value, and the determination is made based on the comparison result. 3) A cell subtraction memory (4) for storing the first specific value for each VCI of the cell is provided, and the period subtraction circuit (2) stores the first specific value for each VCI in the cell counter memory. 3. The ATM cell inflow regulating system according to claim 1, wherein the method is to subtract from the counter value stored in step (1).