JPH0446462A - Area recognizing system for picture processor - Google Patents

Abstract

PURPOSE:To enable a process without reproducing the notches or the projecting and recessing parts at the outer peripheral part of a marking by detecting the marking from a picture data by a marking detecting circuit, and judging to which of the outside, upside, or inside of a closed area, a object picture element belongs by a closed area recognizing circuit. CONSTITUTION:A marking circuit 1 is composed of a concentration detecting circuit 1a, threshold level setting circuit 1b, noise eliminating circuit 1c, and line memory 1d. When the picture element data of an (n)th line being the output of the concentration detecting circuit 1a is inputted to a shift register 13, the picture data is outputted from the register 13 to an AND gate 14. The outputs of the AND gate 14 and of an AND gate 17 are inputted to an AND gate 18, and a mark signal Ca is outputted from this AND gate 18. This mark signal C1 is inputted to a recognition circuit 2a which recognizes to which of the outside, upside, or inside of the said marking, the object picture element belongs.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to an area recognition method for an image processing device, and is used to identify not only a closed area of an unspecified arbitrary shape but also a rectangular area that is inscribed or circumscribed within the closed area. This invention relates to an area recognition method for an image processing device that can perform

(Prior Art) In recent years, image processing devices such as copying machines and facsimile machines have been developed that are capable of performing various types of image conversion, editing, and other processing on a partial area of a document.

As an example of the area recognition method of this image processing device, markings are made on the surface of the document using a marker pen, etc., and after reading this from the input section of the image processing device, the marks are detected.
There is one that recognizes closed areas.

This method can be used to recognize closed regions with complex shapes.
Although it is easy to misrecognize a region, in principle it is possible to recognize a closed region of any shape.

(Problem to be solved by the invention) However, since the markings used in this method are generally handwritten, the periphery of the marking has an uneven shape, and depending on the type of image processing, the periphery of the area There was a problem in that burrs appeared on the parts, making them unsightly.

For example, as shown in Figure 18, if the character B written on the manuscript is marked, the content of image processing is (a
), jaggies will not appear on the periphery of the area, but if the black and white inversion process in (b) or the halftone dotting process in (c) is used, jaggies will appear on the periphery of the area. Become.

Further, although this conventional method has the advantage of being able to perform area recognition and image processing simultaneously in real time, there is a problem in that there is a limit to the processing content that can be realized because the area position is unknown in advance.

For example, there was a problem in that some extracted parts could not be moved to another position and reproduced.

It is an object of the present invention to provide an area recognition method for an image processing device that eliminates the problems of the conventional method described above and allows a designated area to be extracted linearly and neatly even if a document has uneven markings. There is a particular thing.

Another object of the present invention is to provide an area recognition method for an image processing apparatus that allows the position and shape of a designated area to be known in advance of a processing operation.

(Means and Effects for Solving the Problems) In order to achieve the above object, the present invention provides a circuit for detecting markings from image data read by an image input section, a line to which the pixel of interest belongs, and a line before the pixel. A closed area recognition circuit that determines whether the pixel of interest belongs outside, above, or inside the closed area formed by the marking based on the determination result of adjacent pixels; The present invention is characterized in that it includes means for detecting a rectangular area that is in contact with the marking, and means for outputting a signal having the same content as inside the closed area of the marking to an area outside the closed area of the marking and inside the rectangular area.

In the present invention, a marking detection circuit first detects a marking from image data, and then the closed area recognition circuit determines whether the pixel of interest belongs outside, above, or inside the closed area formed by the marking. Ru.

Next, a rectangular area circumscribing or inscribing the closed area of the marking is detected, and a signal having the same content as inside the closed area of the marking is output to an area outside the closed area of the marking and inside the rectangular area. As a result, the rectangular area can be made equivalent to the closed area of the marking, and black and white inversion and halftone dot can be applied to the marking area without being aware of unevenness, jaggedness, etc. around the marking written on the document. Any processing such as can be performed.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a schematic block diagram of one embodiment of the invention.

In the figure, l is a marking detection circuit that detects preset markings from image data V1 sent from the image input unit, and 2 is an area recognition unit that recognizes a designated area based on the output of the detection circuit 1. . Further, 3 is an image memory that stores the recognition result of the area recognition unit 2 in a two-dimensional area, 4 is a rectangular coordinate address detection unit that detects the position coordinates of a rectangular shape adjacent to the recognition area based on the data of the recognition result, and 5 is a The address register 12 that stores the detected address is a rectangular area signal generation circuit that outputs, for example, a signal of "1" to the rectangular area determined by the detected address.

Further, reference numeral 6 denotes a rectangle for correcting a signal from an arbitrary shape to a rectangular shape based on the rectangular area signal from the rectangular area signal generation circuit 12 when outputting the region recognition result of the arbitrary shape stored in the image memory 3. a correction circuit; 7 is an output switching circuit that selects and outputs either an arbitrary shape output or a corrected rectangular shape output; 8 is a circuit that accesses the image memory 3, the rectangular coordinate address detection section, the address register 5, etc.; This is the system control unit that performs control.

Further, reference numeral 9 denotes an image processing section that performs processing such as deletion, black and white inversion, halftone dotting, etc. on the image data v1 based on the output from the output switching circuit 7.

FIG. 2 shows a detailed block diagram of FIG. In the figure,
The same reference numerals as in FIG. 1 indicate the same or equivalents.

The marking circuit 1 is composed of a concentration detection circuit 1as, a threshold level setting circuit 1b, a noise removal circuit IC, and a line memory 1d.

The density detection circuit 1a is a circuit that detects a set gray level between white and black, which is the density of the marking. As shown in FIG. 3, this circuit can be constructed of two comparators whose reference values are two threshold levels (THI, TH2) and a gate that takes the AND of their outputs.

When the density detection circuit 1a detects marking, it outputs a high (H) level signal CO.

This signal CO is input to the noise removal circuit 1c.

An example of the noise removal circuit 1c is shown in FIG. 4(a).

In this circuit 1c, the concentration detection circuit 1a receives an input signal v
This is a circuit for removing portions that are not markings that are erroneously detected as markings due to noise components included in the first image and intermediate density levels occurring at image edge portions. The principle is that marking is determined to be correct only when the detection results of the density detection circuit 1a are detected continuously in the main scanning direction and the sub-scanning direction.

For example, as shown in FIG.
．． D22, D23, D31SD32 and D33 9
This circuit outputs the mark signal C1 only when all pixels are determined to be markings, and determines that the pixels are noise if even one pixel is included that is not determined to be markings.

Now, when the pixel data D33 of the nth line, which is the output of the density detection circuit 1a, is input to the shift register 13,
Pixel data D31 to D33 are output from the shift register 13 to the AND gate 14.

On the other hand, the two line memories 15 have (n-2) lines,
The pixel data that is the output of the density detection circuit 1a of the (n-1) line is stored, and the shift register 16 outputs the (
n-1) line of three pixel data D21-D23, (
Three pixel data DIl to DIB of line n-2) are output to the AND gate 17. Next, the outputs of the AND gates 14 and 17 enter an AND gate 18, which outputs a mark signal C1.

This mark signal C1 is input to a recognition circuit 2a that recognizes whether the pixel of interest belongs outside, above, or inside the marking.

A specific example of the recognition circuit 2a and line memory 2b is shown in FIG. 5(a).

The recognition circuit 2a includes a determination ROM 21, a latch circuit 22, and an address counter 23.

This recognition circuit 2a receives the mark signal CI and a line clock (LINE clock) having a waveform as shown in FIG.
CL)(), a line selection signal (L-8EL), and a pixel clock (PIX-CLK) are input.

Now, n shown in FIG. 7 is stored in the judgment ROM 21.
Assuming that the mark signal CI corresponding to the A pixel of the line is input, the line selection signal (L-8EL) input to the terminal IN4 of the determination ROM 21 is at a high (H) level, so the processing mode of the determination ROM 21 is set to Operates in 1 mode. In this first mode, while reading the n-th line, the contents of the line memory 3 holding the final result of the (n-2) line, the data of the previous pixel of the n-th line currently being input, and the data currently being input Based on the content of the detection data, a provisional primary determination result is obtained and a process is performed to store it in the line memory 2b.

In the first mode, the determination ROM 21 obtains the provisional primary determination result based on the table shown in FIG. FIG. 8(a) is a table applied when the mark signal C1 corresponding to pixel A in FIG. 7 is 0, and n-2
The final result of the corresponding pixel C of the line (horizontal opening of the table),
This table determines the provisional primary determination result of the pixel A, depending on the provisional primary determination result of the previous pixel B (vertical 111II of the table) in n lines. Also, the same figure (b)
is a table that is applied when the mark signal CI corresponding to the A pixel is 0.

In the above table, 0, ■, and M are usually expressed as 2-bit data, where 0 is outside the marking, ■ is inside the marking, M is above the marking, and X is outside, inside, and above the marking. This shows that is indeterminate.

For example, when A-0, if C is 0 (outside) and B is 0 (outside), the tentative primary judgment result for A is O (outside), and C is 1
(Middle), if B is M (Top), the provisional primary determination result of A is l (Medium). Further, if it is A-1, it can be assumed that it is above the marking regardless of the tentative primary determination results of C and B, so the tentative primary determination result of A is M (top).

Note that when the pixel data of ASB%C is made to correspond to the signals of the circuit in FIG. 3 becomes the signal input to the terminal INS.

By the above operation, when the processing in the first mode is completed for the n-th line, the data of the provisional primary judgment result of the second line in FIG. 7 is stored in the line memory 3. . At this time, the line memory 2b outputs the final data rl and r2 of the n-2 line (see FIG. 6).

Next, in the time period of line n+1 in FIG. 6, the line selection signal (
L-8EL) changes to LOW (L). As a result, the judgment R
OM21 moves to the second mode of operation.

The second mode is a mode in which the temporary result data stored in the line memory 2b is converted into a final result based on the relationship between adjacent pixels.

In this mode, the address counter 23 is in the down mode, so the address in the line memory 2b changes in a decreasing direction.

That is, the operation of converting the n lines of temporary data shown in FIG. 9 into the final result proceeds in the direction of the arrow in the same figure. Moreover, in the second mode.

The determination ROM 21 performs the conversion using the table shown in FIG.

The horizontal spread in FIG. 10 shows the data of the final result of the pixel E on the right of the pixel of interest (D in FIG. 9), and the vertical spread shows the data of the tentative primary determination result of the pixel of interest.

Then, the final result for the pixel of interest is determined from the relationship between these two data.

For example, if the final result of pixel E is O (outside) and the tentative primary judgment result of pixel of interest p is M (top), the final result of the pixel of interest is M (top), and the final result of pixel E is is M (top)
If the tentative primary determination result of the pixel of interest is X (indeterminate), the final result of the pixel of interest @D is I (medium).

Furthermore, if the pixel data of H is made to correspond to the signal of the circuit shown in FIG.
1 terminal] corresponds to the signal input to N3, and E is the latch 2 terminal.
2 to the terminal IN2.

Since the rightmost pixel of line n in FIG. 9 is always outside the marking, the final result for this pixel is 0 (outside). Therefore, the final result of the pixel one position left from the rightmost end of this n line is determined based on the table in Figure 10 from the final result of this rightmost pixel and the temporary data of the pixel one position left from the rightmost end. Desired. Thereafter, the temporary data of the pixels of n lines are sequentially converted into the final result.

As a result of the above operations, the processing mode becomes the second mode during the time period of the (n+1) line in FIG.
The final result data of n lines is stored in the memory 2b, and the temporary data of n lines is output from the line memory 2b.

From the above, according to this embodiment, one result is obtained while repeating two processes for every l line. Therefore, as is clear from the output data rl and r2 of the line memory 2b in FIG. 6, final data and temporary data are alternately output for each line.

The output data "1, r2" of the line memory 2b is sent to the data compression circuit 11 and the rectangular coordinate address detection circuit 4.

The data compression circuit 11 compresses the output data rl and r2 indicating the determination result by area recognition, reduces the amount of data, and stores it in the image memory 3. Note that if a large capacity memory is used as the image memory 3, the data compression circuit 11 is not necessary.

On the other hand, the output data r1 and r2 sent to the rectangular coordinate address detection circuit 4 are input to the OR gate of the circuit shown in FIG. 11, for example. Here, FIG. 11 shows a specific example of the rectangular coordinate address detection circuit 4.

In the figure, 41.42 is the signal “
a multiplexer which selects the A terminal input when a signal "0" is applied and selects the B terminal input when a signal "1° is applied;
is an address register 44 that latches input data D1 at an address determined by 4-bit addresses AO to A3.
45 is a comparator that compares two inputs A and B, and 45 selects the A terminal input when the signal "0" is applied to the selection terminal (SEL), and selects the B terminal input when the signal "1" is applied. This is a multiplexer that selects the input. Further, 46 is a timing generator, and 47 is an address control circuit.

In this embodiment, it is possible to detect up to four rectangular areas. Therefore, address register 5
As mentioned above, the address number is 4 bits, and the lower 2 bits control the address value ■in s wax s and XSY, and the upper 2 bits control the number of channels.

FIG. 12 shows an example of memory allocation for the address register 5. From this example, address AO is 1111
It is clear that the address AI represents the distinction between %■aX, the address AI represents the distinction between X1Y, and the addresses A2 and A3 represent the distinction between the number of channels.

Next, the operation shown in FIG. 11 will be explained with reference to FIG. 13. The symbols in FIG. 13 correspond to those in FIG. 11.

When the output data rl and r2 are input to the OR gate 48, the combined signal rl+r2 is input to the timing generator 46. Further, a system clock and a line clock are input to this timing generator 46. The example in which the composite signal rl+r2 is input to the timing generator 46 is for detecting a rectangular area circumscribed to a marking, and when detecting a rectangular area inscribed to a marking, the timing generator 46 It is sufficient to apply only the output data r2 to the device 46.

The timing generator 46 outputs a memory chip select signal of a predetermined length in synchronization with the rising and falling edges of the composite signal rl+r2. On the other hand, address control circuit 47
At first, the “0” signal is output from the AI terminal, so
The multiplexer 41 selects the X address input to the A terminal, and this X address value is sent to the address register 5.
is stored at address (0000).

Next, when the "1° signal is output from the A1 terminal of the address control circuit 47, the multiplexer 41 selects the Y address input to the B terminal, and this Y address value is set to (0010) of the address register 43. Stored in address.

Next, when the composite signal rl+r2 falls, the "0" signal is output from the A1 terminal of the address control circuit 47, so the multiplexer 41
An address is selected, and this X address value is stored at address (0001) of the address register 5.

Marking Xm1n as described above.

Once the initial values of X wax and Ymin are set, from now on, a new multiplexer
Xm1n of the marking of the X address value input to 1
−5XIlax − and the initial value X1llnsXlax
is compared by the comparator 44, and X1in <Xm1n
If so, the data at the address (0000) is X5in
-, and if Xm1n -≧X1n, the data at the address (0000) is not updated and is maintained. Also, if Xaax −>Xff1ax, the data at the address (0001) is updated to Xmax −, and Xm
If ax −≦X wax, the data at address (0001) is not updated and is maintained.

On the other hand, the initial value Yein is maintained without being updated, and Y wax detected after the second line in the main scanning direction is updated line by line, and this update is continued unconditionally until marking detection is completed. Ru.

As described above, for example, the first
In the case of marking 49 shown in Figure 4, the final
m1n −Xs, Xmax = X2°, Ysin −
YI SYmax-Yn is detected.

In addition, in FIG. 13, the memory write enable (W
E) The output of the comparator 44 is the marking Xm1n
, is output only when it is determined that it is necessary to update Xmax.

Minimum and maximum values in the X and Y directions of the marking determined as above X■1n s X5ax sYmln
and Y wax are sent to the rectangular area signal generation circuit 12.

FIG. 15 is a circuit diagram showing a specific example of the rectangular area signal generation circuit 12. As shown in the figure, the rectangular area signal generating circuit 12 receives Xm from the address register 5.
1n (XI), Xmax (X2), Ymin
(Yl), Ymax (Y2), and four comparators that receive X and Y address counter data as inputs, and an AND gate. Therefore, according to this circuit, "1" is inside the rectangular area circumscribing the marking.
, a rectangular area signal S3 of "θ" is output outside the rectangular area. This rectangular area signal S3 is input to the rectangular correction circuit 6.

FIG. 16 shows an example of this rectangular correction circuit 6. As shown in FIG. 17, the rectangular correction circuit 6 performs a process of outputting the same signal S2 as inside the marking to an area outside the marking and inside the rectangular area S3. As a result, the 17th
As shown in the figure, a signal S2 is output inside and outside the marking and within a rectangular area S3, and a signal S1 is output above the marking.

The area signal from the image memory 3 and the area signal from the rectangle correction circuit 6 are input to an output switching circuit 7 and selected by a selection signal from a system control circuit 8. For example, when the image processing section 9 (see FIG. 1) performs black and white inversion or halftone dot processing on the marking section, the output switching circuit 7 selects the output of the rectangle correction circuit 6 and outputs the signal SL +82. The black and white inversion or halftone dot processing is performed on the area. As a result, this processing is applied to a rectangular area, so even if there are burrs around the markings on the document, these will not appear in the output after image processing, and the processing can be performed cleanly. .

Further, according to this embodiment, since the shape of the marking is known in advance, it is possible to perform various processes on the document information.

Incidentally, in the above embodiment, the operation was explained in the case of detecting a rectangular area circumscribed to a marking, but the operation is also performed to detect a rectangular area inscribed in a marking and output the signal S2 only within the rectangular area. Of course, you may do so.

(Effects of the Invention) As is clear from the above description, according to the present invention, it is possible to perform editing processing such as inverting black and white or halftone dotting on the rectangle circumscribing the marking, so that the outer periphery of the marking can be jagged. Alternatively, even if there are irregularities, it can be processed without reproducing them.

Further, for this reason, there is an advantage that accuracy is not required in the marking work on the document, and marking can be performed easily and casually.

Furthermore, since the shape of the marking is known in advance, various processes can be performed on the document information.

For example, it is possible to move a partially extracted image, or to move multiple regions to different positions and re-edit them.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a detailed block diagram of the main parts of the embodiment, FIG. 3 is a circuit diagram showing an example of a concentration detection circuit, and FIG. FIG. 5 is a circuit diagram showing a specific example of a noise removal circuit, FIG. 5 is a circuit diagram showing a specific example of a recognition circuit, FIG. 6 is a time chart of signals of the main part of the recognition circuit, and FIG. 7 is a circuit diagram showing a specific example of the recognition circuit. FIG. 8 is a diagram showing the determination table of the first mode, FIG. 9 is an explanatory diagram of the operation of the recognition circuit in the second mode, and FIG. 10 is the determination table of the second mode. Diagram showing the table, No. 11
The figure is a circuit diagram showing a specific example of a rectangular coordinate address detection circuit, and FIG. 12 is a diagram showing the memory allocation of the address register.
FIG. 13 is a time chart of signals of the main parts of the rectangular coordinate address detection circuit, FIG. 14 is a conceptual diagram of the operation of the rectangular coordinate address detection circuit, and FIG. 15 is a specific example of the rectangular area signal generation circuit. FIG. 16 is a circuit diagram showing a specific example of a rectangle correction circuit, FIG. 17 is a conceptual diagram of the operation of the rectangle correction circuit, and FIG. 18 is a diagram showing an example of processing of a conventional marking section. DESCRIPTION OF SYMBOLS 1... Marking detection circuit, 2... Area recognition part, 4
... rectangular coordinate address detection section, 5 ... address register, 6 ... rectangle correction circuit, 7 ... output switching circuit,
9... Image processing unit, 12... Rectangular area signal generation circuit, Agent Patent attorney Michito Hiraki and one other person (a) (a) (1st mode) (1st mode) (1st mode) (1st mode) (1st mode) (1st mode) fig. fig. zu Ayo C (C) rep, ji 1

Claims (1)

[Claims] (1) A circuit that detects markings from image data read by an image input unit; a closed area recognition circuit that determines whether the area belongs outside, above, or inside the area; means for detecting a rectangular area that is circumscribed or inscribed in the closed area of the marking; Area recognition for an image processing device, characterized in that it is capable of recognizing a rectangular area that is circumscribed or inscribed in the closed area of the marking, comprising: means for outputting a signal having the same content as in the closed area of the marking to the area; method.