JPH0446490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a D/A converter response test device, and more particularly, to a device suitable for a high-speed D/A converter response test. It is something.

(Prior Art) FIG. 3 is a block diagram showing an example of a device for testing the response characteristics of a conventional D/A converter. Third
In the figure, numeral 1 denotes a pattern generator that generates digital pattern data, and generates digital pattern data D ₁ to be applied to a D/A converter to be evaluated (hereinafter referred to as a D/A converter) 2 . A comparator 3 compares the analog signal AS converted and output from the D/A converter 2 with the reference voltage Vr output from the reference voltage generator 4, and its output signal is held by the flip-flop 5. 6 is a timing signal generator that outputs a timing signal for controlling the operation of each part. That is, the pattern generator 1 alternately generates digital pattern data corresponding to the first level and digital pattern data corresponding to the second level as digital pattern data D ₁ according to the timing signal TS ₀ applied from the timing signal generator 6. The D/A converter 2 converts the digital pattern data _D1 into an analog signal AS in accordance with the timing signal TS1 applied from the timing signal generator 6, and converts the digital pattern data _D1 into an analog signal AS.
is the comparator 3 at that point in time according to the timing signal TS ₂ applied from the timing signal generator 6.
Holds the output signal.

FIG. 4 is a timing chart for explaining the operation of FIG. 3. In FIG. 4, a indicates digital pattern data _D1 output from the pattern generator 1 to the D/A converter 2, and corresponds to the full scale input of the D/A converter 2 as the first level, for example. data X and the second
As a level, data X' corresponding to zero input is alternately output in each cycle. Each of these data X,
According to the timing signal TS ₁ shown in b applied to the D/A converter 2 from the timing signal generator 6, X' is converted to C by the D/A converter 2 after a predetermined time Td has elapsed from the rise of the timing signal TS ₁ . It is converted into an analog signal AS as shown in . This analog signal AS is applied to the reference voltage generator 4 by the comparator 3.
It is compared with the DC reference voltage Vr output from the DC reference voltage Vr.
The output signal of the comparator 3 is sent to the timing signal generator 6.
The flip-flop 5 sequentially holds the flip-flop 5 according to the timing signal TS2 shown at d applied from the flip-flop ₅ .
As a result, the output signal of flip-flop 5
OUT will change every timing signal TS ₂ as shown in e.

(Problem to be Solved by the Invention) However, according to such a configuration, the output signal OUT of the flip-flop 5 is a timing signal.
Since it changes every _TS2 , it is necessary to constantly monitor the output signal OUT of the flip-flop 5 at each timing, making it difficult to perform a characteristic test of high-speed conversion operation.

The present invention has been made with attention to such points, and its purpose is to have a relatively simple configuration,
An object of the present invention is to provide a device capable of performing a dynamic response test of a D/A converter that performs high-speed conversion.

(Means for Solving the Problems) The present invention achieves the above object by providing digital pattern data representing the first level corresponding to the full scale input applied to the D/A converter under test and corresponding to the zero input. Digital pattern data representing the second level is output alternately every cycle, and the comparator performs a comparison operation for either the first level conversion output or the second level conversion output of the D/A converter under test. A pattern data generator that generates digital pattern data to be selectively prohibited; and a DC reference voltage corresponding to the first level and second level of the digital pattern data applied from the pattern data generator to the D/A converter under test. a reference voltage generator that selectively switches and outputs the voltage in conjunction with switching to prohibit the comparison operation of the comparator; and analog signals converted by these D/A converters to be tested and output from the reference voltage generator. The present invention is characterized in that it is comprised of a comparator that compares the voltage with a reference voltage, and a latch circuit that holds the mismatch output of the comparator as a D/A conversion response malfunction detection signal of the D/A converter under test.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. In FIG. 1, along with first level and second level digital pattern data D ₁ that is applied from a pattern data generator 1 to a D/A converter 2,
It is added to the comparator 3 in order to prohibit the operation of comparing either the zero output level (second level) or the full-scale output level (first level) of the D/A converter 2 with a predetermined reference voltage Vr. Digital pattern data _D2 is output. The reference voltage generator 4 receives data from the pattern data generator 1 from D/
A DC reference voltage is selectively switched and output in accordance with the first level and second level of the digital pattern data applied to the A converter 2 in conjunction with the switching of prohibition of the comparison operation of the comparator 3. 7 is a D/A converter that outputs a mismatch output with a predetermined reference voltage Vr for either the zero output level or the full case output level of the D/A converter 2 compared by the comparator 3.
This is a latch circuit that holds the D/A conversion response malfunction detection signal of the converter.

FIG. 2 is a timing chart for explaining the operation of FIG. 1. Note that the response test after switching to inhibit the comparison operation of the comparator 3 is performed after a sufficient period of time has elapsed for the circuit to stabilize. In FIG. 2, a is from the pattern data generator 1 to D/
Digital pattern data output to A converter 2
D ₁ and b is the timing signal TS ₁ applied from the timing signal generator 6 to the D/A converter 2.
, c indicates the analog signal AS converted and output from the D/A converter 2, and d indicates the timing signal _TS2 applied from the timing signal generator 6 to the latch circuit 7. e is the pattern data generator 1 in order to prohibit the operation of comparing the zero output level of the D/A converter 2 with a predetermined reference voltage Vr.
is the digital pattern data _D2 applied to the comparator 3 from . That is, in the period in which the digital pattern data _D2 is at H level, a comparison operation is performed between the full case output level (first level) and the predetermined reference voltage Vr. f indicates data OUT which is latched by the latch circuit 7 and output to the outside. Here, the latch circuit 7 outputs the analog signal AS converted by the D/A converter 2 at time _t1 .
If the level of the reference voltage Vr exceeds the level of the reference voltage Vr, it is assumed that the _two signals match and the comparison output data is not latched. If the level of the signal AS has not reached the level of the reference voltage Vr, it is assumed that the two signals do not match, and the comparison output data is latched. The data OUT thus latched is held until a clear signal is applied.

In this way, since the latch circuit 7 holds the detection signal of the D/A conversion response malfunction of the D/A converter 2, there is no need to judge the comparison result of the comparator every cycle as in the conventional case. , conversion speed is 100MHz
The dynamic response characteristic test of a high-speed D/A converter as described above can also be easily performed. That is, according to such a configuration, when the digital pattern data D1 input to the D/A converter ₂ changes between the first level and the second level,
A defect in the transition operation of the A converter 2 can be reliably latched.

In the above embodiment, the timing signal TS ₂ is applied from the timing signal generator 6 to the latch circuit 7 once per cycle, so that the output signal D ₂ of the pattern data generator 1 is used to control the output of the D/A converter 2. Although an example has been shown in which the comparison operation of the comparator 3 for the second level zero conversion output is masked, the timing signal applied from the timing signal generator 6 to the latch circuit 7 is
It may be controlled so that TS ₂ is added once every two periods.

Further, the comparison operation of the comparator 3 with respect to the first level full case conversion output of the D/A converter 2 may be masked.

(Effects of the Invention) As explained above, according to the present invention, it is possible to realize a D/A converter response test device that can perform a dynamic response test of a D/A converter that performs high-speed conversion with a relatively simple configuration. , the practical effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an example of a conventional device, and FIG. 4 is a timing chart for explaining the operation of FIG. 3. DESCRIPTION OF SYMBOLS 1... Pattern data generator, 2... D/A converter, 3... Comparator, 4... Reference voltage generator, 6... Timing signal generator, 7... Latch circuit.

Claims (1)

[Claims] 1. Digital pattern data representing a first level corresponding to a full-scale input applied to a D/A converter under test and digital pattern data representing a second level corresponding to a zero input are alternately provided in each cycle. Pattern data generation that generates digital pattern data that selectively inhibits the comparison operation of the comparator for either the first level conversion output or the second level conversion output of the D/A converter under test. and direct current reference voltages corresponding to the first level and second level of the digital pattern data applied from the pattern data generator to the D/A converter under test in conjunction with switching to prohibit the comparison operation of the comparator. a reference voltage generator that selectively switches and outputs the output; a comparator that compares the analog signals converted by these D/A converters under test with the DC voltage output from the reference voltage generator; 1. A D/A converter response test device comprising: a latch circuit that holds a mismatch output as a D/A converter response malfunction detection signal of a D/A converter under test.