JPH0446527A - Controlling method for current of harmonic wave suppressor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention uses a current binary width control method (also called a hysteresis comparator method) of the so-called instantaneous current value control method to control harmonic current in the load current of a grid power supply through a semiconductor power conversion device (for example, a voltage bridge inverter device). The present invention relates to a method for controlling an output current in a harmonic suppression device that suppresses the output current. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 2 is a block circuit diagram showing the main part configuration of a conventional harmonic suppression device using an instantaneous current value control method. In the figure, 1 is the system power supply, 2 is the 3-phase power system line, IL (ILR, iLs, ILT) is the system load current flowing in the R phase, S phase, and T phase of this power system line 2, and 3 is the load current ILR of each system. This is a current detector that detects ILS and ILT. 4 are R and S that should be left in the power supply system line 2 from each system load current ILR, ILS, and ILT, respectively. Fundamental wave current 11 (ia
This is a three-way harmonic calculation circuit that extracts 1, ibL 1cl). Note that this triad harmonic calculation circuit 4 can generally extract any desired harmonic component by specifying the calculation method. 5 (5a, 5b, 5c) are adders for each phase of R, S, and T, respectively, and the fundamental wave currents i al and i
System load current ILR, ILS, IL from bLicl
By subtracting T, this system load current I LR, I LS,
The harmonic current that should be removed (suppressed) from the ILT is determined by the harmonic current command i ” (i a , i b ”,
8 is the harmonic current for each phase of R, S, and T corresponding to the current commands ia", tb", and ic (referred to as converter output current) i (ia, ib, ic) and injected into each phase R, S, and T of the power system line 2 so as to cancel out the harmonic currents in the system load currents ILR, ILS, and ILT. In this example, the semiconductor conversion device is a voltage type bridge inverter. 9 is a current detector that detects the output current 1 (ia, ib, ic) of this semiconductor conversion device 8, respectively; 6 (6
a, 6 b, 6 c) are each harmonic current command i
a”, i b”, i c” and converter output current i
Deviation current Δi (Δia,
7 (7a, 7b, 7c) are deviation currents Δfa, respectively. Δib, Δic are within a predetermined tolerance range (for example, ± of the rated current)
1%), a comparison device (C
(also abbreviated as P). Each of the comparators 7, for example 7a, is a comparator (not shown) that compares the deviation current Δia with a positive standard deviation +εl created from the standard deviation ε1, and also a comparator (not shown) that compares the deviation current Δia with a positive standard deviation +εl created from the standard deviation ε1. It consists of a comparator (not shown) that compares with the negative standard deviation -ε1, and when the converter output current ia decreases and the deviation current Δia exceeds the positive standard deviation +ε1, the Comparator output 1 indicating that the upper arm corresponding to the R phase of the bridge-connected semiconductor switching element should be turned on (the lower arm should be turned off)
At this time, the voltage of a DC power supply (not shown) in the semiconductor conversion device 8 is applied as a positive voltage to the R phase of the power supply system line 2. ), the converter output current ia is switched in the increasing direction. Conversely, due to an increase in the converter output current ia, the deviation current ia
is less than the negative standard deviation -ε1, the comparator 7
a outputs a comparator output 11 indicating that the upper arm of the bridge connection should be turned off (the lower arm should be turned on). The voltage is applied as a negative voltage. )
, switches the converter output current ia in the decreasing direction. In this way, so-called binary current width control is performed so that the deviation current Δia falls within the standard deviation ±ε1 (the range of this standard deviation is also referred to as a binary width). Note that the operations of the comparators 7b and 7C are also similar to that of the comparator 7a. Also, in the above example, the positive and negative standard deviations are ε1. −ε1
The absolute values of are equal, but in general there is no need for them to be equal.

[Problem to be solved by the invention]

1) Regarding the first invention: In the conventional current instantaneous value control type harmonic suppression device, as described above, the two values of positive reference deviation +εl and negative reference deviation -ε1, which are the standards of the comparator in the comparator 7, cannot be converted. It was set as a fixed value determined from the capacitance of the device 8 and the switching frequency of the semiconductor. Therefore, when the system load current becomes a light load, the magnitude of the current command Bi at that time also becomes small, so the ratio of the standard deviation ε1 to this small current command becomes large, and therefore, the current command i*
There is a problem in that the waveform followability of the converter output current i with respect to the current command 11 deteriorates depending on the magnitude of the current command 11. Therefore, an object of the first invention is to provide a current control method for a harmonic suppression device that can obtain good waveform followability regardless of the magnitude of the current command. 2) Regarding the second invention: Also, when the power supply is lightly loaded, the magnitude of the harmonic current to be suppressed becomes small, and the deviation current Δi changes to the standard deviation (current binary width) by turning on and off the semiconductor switching element in the semiconductor converter 8. ) The time to reach ±ε1 is also shorter,
There is a problem in that the switching frequency of the comparator output 11 (the switching frequency of the semiconductor switching element) increases, and as a result, the loss of the snubber circuit added to the semiconductor switching element becomes excessive. Therefore, an object of the second invention is to provide a current control method for a harmonic suppression device that can solve this problem.

[Means to solve the problem]

In order to solve the above problem, harmonic current (harmonic current command i ” (ia”
. 1b"+IC"), etc. (current detector 3, three-phase harmonic calculation circuit 4, adder 5, etc.) and a semiconductor switching element to detect a current equal to the detected harmonic current. (such as i (ia, ib, ic), hereinafter referred to as converter output current) and injects the harmonic current into the grid power supply so as to cancel the harmonic current, the power converter includes an adder 6 (6a, The deviation current (Δi (Δia
. In a harmonic suppression device comprising a power conversion device (semiconductor device 8, etc.) that turns on or off the semiconductor switching element (based on), the method of the first invention comprises: ) The standard deviation ε is proportional to the magnitude of the detected harmonic current.
2, etc.) is added to the allowable limit value (via an adder 23, etc.) so as to increase its absolute value, and the method of the second invention includes (F/V converter 22, etc.). A value (standard deviation ε3, etc.) proportional to the semiconductor switching frequency (obtained via an adder 23, etc.) is added to the allowable limit value so as to increase its absolute value (via an adder 23, etc.) shall be.

[For use]

■) Regarding the first invention: By increasing or decreasing the size of the standard deviation (current binary width) according to the magnitude or small of the harmonic current command, the size of the standard deviation seen from the current command value when the grid power supply is lightly loaded can be changed. is made smaller than before, and the waveform followability of the converter output power source with respect to the harmonic current command is improved. 2) Regarding the second invention: By increasing or decreasing the magnitude of the standard deviation depending on whether the switching frequency of the semiconductor conversion device is large or small, an excessive rise in the switching frequency during a light load on the grid power supply is suppressed.

【Example】

FIG. 1 is a block diagram showing the main structure of a harmonic suppression device as an embodiment of the present invention, and corresponds to FIG. 2. In Fig. 1, in contrast to Fig. 2, the harmonic components contained in the grid current are calculated from the three-phase load current I L (I LR, I LS, I LT) detected from the grid power supply l. Find the effective value of the semiconductor converter output current command 10 and calculate the standard deviation (voltage)
The standard deviation (
The F/V converter 22 outputs as voltage) ε3, and the standard deviation ε1. Standard deviation ε2 and F/ as the output voltage of the effective value calculator 21
An adder 23 is newly installed which adds the standard deviation ε3 as the output voltage of the V converter 22 and provides it to the comparator 7 (7a, 7b, 7c) as a new standard deviation for comparison. In this case, a comparison device? In the comparators (7a, 7b, 7c), the deviation current Δi (Δia, Δib, Δic,
), the positive standard deviation is +(ε1
+ε2+ε3), and the negative standard deviation is -(ε1+ε
2+ε3). Therefore, when the grid power supply is lightly loaded, the effective value calculator output voltage ε2 becomes smaller than when the rated load is applied, so by reducing the absolute value εl+ε2+ε3 of the standard deviation, the standard deviation for the light power system load current IL at this time can be reduced. The ratio is also smaller than in the past, and the waveform followability of the converter output current i with respect to the current command 50 is improved. In addition, when the power supply is lightly loaded, the influence of the output of the converter 8 on the power supply line 2 increases relatively, so the frequency of change of the binary values of the comparator output 11 increases, and the F/V
As the output voltage ε3 of the converter 22 increases compared to the rated load of the grid power supply, the absolute value of the standard deviation εl+ε2+ε3
It is possible to increase the frequency of change in the comparator output 11, thereby suppressing an increase in the switching frequency of the semiconductor element, and to prevent an excessive increase in the loss of the snubber circuit added to the semiconductor switching element.

【Effect of the invention】

In the harmonic suppression device using the current instantaneous value control method, this first
According to the invention, the current control binary width (standard deviation) is changed depending on the effective value of the current command to the semiconductor conversion device that injects the harmonic current to be canceled into the grid power supply load current. The comparator operating level can be automatically corrected to improve the followability of the semiconductor converter output current to the current command during light loads. On the other hand, improving the waveform followability will lead to an increase in the switching frequency of the semiconductor, but according to the second invention, the comparator output is F/V converted and the converted voltage is added to the standard deviation. As a result, the switching frequency of the semiconductor element is suppressed when the system power supply is lightly loaded, and an excessive rise in the temperature of the snubber circuit can be prevented. In this way, the waveform followability of the converter output current is not impaired by the load current on the grid side, and stable operation is always possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main configuration of an embodiment of the present invention, and FIG. 2 is a conventional block diagram corresponding to FIG. 1. 1: System power supply, 2: System line, 3, 9: Current detector,
4: 3 Osho harmonic calculation circuit, 5 (5a, 5b. 5c), 6 (6a, 6b, 6c), 23: Adder, 7 (7a. 7b, 7c): Comparison device, 8: Semiconductor conversion device, 10:
Standard deviation setter, 11: Comparator output, 21: Effective value calculator, 22: F/V converter, I L (I LR, I
L.S. ILT): Grid load current, 1Hial, ibl,
1cl) Two fundamental currents, i ” (i a”, i
b", i c") harmonic current command, Δi (Δia
, Δib, Δic): deviation current, ε1. e2. t3
: Standard deviation (voltage), 1 (ia, ib.

Claims (1)

[Claims] 1) Means for detecting a harmonic current included in a load current of a grid power supply, and generating a current equal to the detected harmonic current (hereinafter referred to as a converter output current) through a semiconductor switching element. A power conversion device that injects the harmonic current into the grid power supply so as to cancel it, wherein the deviation current between the detected harmonic current and the converter output current is a positive or negative predetermined allowable limit value. A harmonic suppression device comprising: a power conversion device that turns on or off the semiconductor switching element whenever the semiconductor switching element attempts to deviate from the range;
The method is characterized in that the absolute value is added to the permissible limit value so as to increase it. A current control method for a harmonic suppressor. 2) A means for detecting harmonic current included in the load current of the grid power supply, and generating a current equal to the detected harmonic current (hereinafter referred to as converter output current) through a semiconductor switching element to the grid power supply. A power converter that injects the harmonic current so as to cancel it, wherein the deviation current between the detected harmonic current and the converter output current deviates from within a predetermined positive and negative allowable limit value range. and a power conversion device that turns on or off the semiconductor switching element each time, the absolute value of which increases a value proportional to the switching frequency of the semiconductor switching element to the permissible limit value. 1. A current control method for a harmonic suppression device, characterized in that the current is added as follows.