JPH044663A - signal generator - Google Patents

Abstract

PURPOSE:To obtain a signal output with high gradation by using a capacitive means inserted in series with a common output line so as to apply subtraction processing to an offset voltage of a buffer amplifier provided in a sensor chip and to eliminate a difference between outputs of the sensor chips. CONSTITUTION:A sum VRES1+VOFF of an output reset voltage VRES1 of a sensor chip C and an offset voltage VOFF of a buffer amplifier A provided in the sensor chip is read at a level of a common output line connecting to a capacitor 3 for an output reset period and the level of the other electrode of the capacitor 3 is set to a reset voltage VRES2 by a reset power supply 5. Succeedingly, a sum VSIG+VRES1+VOFF of an output voltage VSIG from a picture element S provided in the sensor chip and a voltage VRES1+VOFF read for a reset period is read at a CIN for a signal period after the reset period. The operation above is sequentially implemented for each sensor chip and a signal output without a difference between sensor chips is obtained from an amplifier 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal generation device, and particularly to a signal generation device in a photoelectric conversion device having a plurality of sensor chips.

[Prior art] Conventionally, a "tethered sensor" has been used, which connects multiple sensor chips in a photoelectric conversion device to form a single signal generating device.
is constructed as shown in FIG. 2(1), and its operating waveform diagram is shown in FIG. 2(2).

In the second section fil, C is a sensor chip, 1 is a common output line of sensor chip C, 22 is an output section, 42 is a buffer amplifier, S is a pixel, SR is a shift register, and E is a voltage V
RESI pixel output reset power supply, MRES is a switching MO3I-transistor for pixel output reset that opens and closes the reset power supply E with the reset pulse φRES, A is the buffer amplifier, M is the signal output from the sensor chip C that opens and closes with the pulse φ5w. Switching MO5 for
) - is a transistor. Incidentally, to simplify the explanation, the amplification degree of the buffer amplifier 4 is assumed to be 1.

Next, the operation will be explained with reference to FIG. 2 (2). Outputs from pixels S in sensor chip C are sequentially read out to output lines by shift pulses from shift register SR. Here, each time the output from one pixel is read, the output line is reset by the output reset pulse φRES and set to the voltage V*tS+.

Next, this read output is read out to an output line common to all sensor chips via a buffer amplifier A and a switching MOS transistor M. For example, pulse φ
During the period when the switching MOS transistor M1 is conductive due to sw1, the output of the sensor chip C10) is read out to the common output line via the buffer amplifier Al. Subsequently, during the period when the switching MOS I-transistor M2 is conductive due to the pulse ψswz, the sensor chip C
The output from A2 is read out to the common output line via buffer amplifier A2.

In this way, the outputs of the given sensor chips are sequentially read out to the common output line.

[Problems to be Solved by the Invention] However, in the above conventional example, the output line of each sensor chip C is connected to the common output line 1;
However, the stray capacitance of C acts as a large capacitive load on each sensor chip C. Therefore, the output of each sensor chip C has the offset voltage V of the stupid buffer amplifier A of the reset voltage VREI11. FF will be added, and its offset voltage ■. Due to variations in the FF, there is a drawback that steps occur in the output voltage for each sensor chip C, as shown at 52° and S2°ut2 in Figure (B).

This level difference, especially in the dark output, acts as a variation in the output, so it significantly deteriorates the gradation level of the connection sensor.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a signal generating device that does not cause a difference in signal output from sensor chip to sensor chip.

[Means for Solving the Problems] In order to achieve the above object, the signal generating device of the present invention has the following features:
It is equipped with a plurality of sensor chips composed of a plurality of pixels, and an output section that inputs and outputs signals sequentially output from the plurality of sensor chips through a common output line, and the output section capacitor means for inputting the signal through a common output line; an amplifier for inputting and outputting the signal output from the capacitor means; a reset means for resetting the signal input to the amplifier; and switch means that opens and closes in synchronization with the reset frequency of the plurality of pixels.

[Function] The output of each sensor chip is sequentially input to the capacitor means of the output circuit via the common output line, and the offset voltage of the sensor chip is added during the reset period, and the offset voltage is added during the signal period. A signal voltage is input. And during this signal period, on its output side by means of capacitance,
A signal voltage from which the offset voltage has been subtracted is obtained, and therefore, a continuous signal output with no difference in level from sensor chip to sensor chip is obtained as a whole.

Note that the reset voltage applied from the reset means is adjusted in accordance with the subsequent signal processing.

[Example] The present invention will be explained with reference to the drawings.

Figure 1 (1) is a circuit diagram of an embodiment of the present invention, Figure 1 (2) is a circuit diagram of an embodiment of the present invention.
) is the output waveform diagram. In Figure 1 (1), ■
is a common output line of the sensor chain C, 2 is an output section, 3 is a capacitor which is a capacitance means connected in series to the common output line l, 4 is a buffer amplifier with an amplification factor of 1 having a buffer function, and 5 is a reset means Voltage VR): II□ reset power supply, 6 is a pulse φTIE! synchronized with the output reset pulse of sensor chip C. This is a switching MOS transistor which is a switching means that is opened and closed by a switch 1. Note that the sensor chip C has the same configuration as that in the conventional signal generator shown in FIG.

Next, the operation of this embodiment with the above configuration will be explained.

First, during the output reset period, on the side of the capacitor 3 connected to the common output line 1 (hereinafter referred to as the CIN side),
Output reset voltage VRI of sensor chip C! ! + and the offset voltage VOFF of the buffer amplifier A of the sensor chip, V, IESI +VOFF is read out, and the other side of the capacitor 3 (hereinafter referred to as Cout
side) is the reset voltage V□ from the reset power supply 5
Set to 3□: Here, VRESI is common to each sensor chip. Subsequently, during the signal period after the reset period, on the C+N side, the sum of the output voltage VS+a from the pixel S of the sensor chip and the voltage read out during the reset period, VllE91 +VQFF, is
s IG + VREll + VOFF is read. At this time, on the Ca u side, the voltage V*Es+ read out on the C side during the reset period due to capacitive coupling.
The difference from +VOFF, V m+(++VRESl +
VOFF=(VI?E51 + VOFFI ”Vs+
Offset voltage VOFF and reset voltage of a, especially offset voltage ■ that differs from sensor chip to sensor chip. Only the signal voltage Vs+c from which FF is subtracted and removed is obtained. The amplifier 4 is supplied with a voltage that is the sum of the signal voltage V3.6 and the reset voltage ■, 2 from the reset power supply 5.
V! lIQ+VllEs2 is input.

The above operations are performed sequentially for each sensor chip, and from the amplifier 4, a signal output with no step difference for each sensor chip as shown by 5laut in FIG. 1(b) is obtained.

In addition, in the present invention, the reset pulse and reset power source used in the sensor chip can be used as the reset pulse and reset power source for driving the switch means, and a new clock generation source and power source for that purpose can be used. There is no need to provide one, and costs can be reduced.

[Effects of the Invention] As explained above, according to the present invention, the offset voltage of the buffer amplifier of the sensor chip is subtracted by the capacitor means inserted in series in the common output line, and the step difference appearing in the output of each sensor chip is eliminated. By eliminating this, it is possible to obtain a high-gradation signal output, and there is an effect that variations in the output during dark times can be significantly reduced.

Further, since the reference level of the output can be adjusted by the reset means, there is an effect that signal processing matching the level of the subsequent stage can be easily performed.

[Brief explanation of the drawing]

Figure 1 (1) is a circuit diagram of an embodiment of the present invention, Figure 1 (2) is a circuit diagram of an embodiment of the present invention.
) is its output waveform diagram, FIG. 2(1) is a circuit diagram of the conventional signal generator, and FIG. 2(2) is its operating waveform diagram. In the figure, ■ is a common output line, 2.22 is an output section, 3 is a capacitance means (capacitor), 4.42 is an amplifier, 5 is a reset means (reset power supply), and 6 is a switching MO5)
- transistor, C is the sensor chip, and A is the buffer amplifier. Agent Patent Attorney Johei Yamashita

Claims (1)

[Scope of Claims] A signal comprising a plurality of sensor chips composed of a plurality of pixels, and an output section that inputs and outputs signals sequentially output from the plurality of sensor chips through a common output line. In the generator, the output section includes: capacitive means for inputting the signal via the common output line; an amplifier for inputting and outputting the signal output from the capacitive means; and a signal input to the amplifier. A signal generating device comprising: a reset means for resetting; and a switch means for opening and closing the reset means in synchronization with the reset frequency of the plurality of pixels.