JPH0466746U

JPH0466746U -

Info

Publication number: JPH0466746U
Application number: JP11011890U
Authority: JP
Priority date: 1990-10-19
Filing date: 1990-10-19
Publication date: 1992-06-12

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図、第２
図はタイマの正面パネルの概略構成図、第３図は
本考案のタイムチヤート、第４図は従来例のタイ
ムチヤートである。１……ＣＲ発振回路、２……主分周器、８〜１
０……第１〜第３分周器（副分周器）。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a schematic diagram of the front panel of the timer, FIG. 3 is a time chart of the present invention, and FIG. 4 is a conventional time chart. 1...CR oscillation circuit, 2...Main frequency divider, 8-1
0...First to third frequency dividers (sub frequency dividers).

Claims

[Claims for Utility Model Registration] An oscillation circuit 1 that outputs a pulse with an oscillation frequency according to a setting operation, and a main frequency divider 2 that divides the frequency of the pulse, the main frequency divider 2 being installed inside an IC. In the electronic timer configured, sub frequency dividers 8 to 10 that divide the frequency of the pulse at a frequency division ratio different from that of the main frequency divider 2 are additionally configured inside the IC, and the main frequency divider 2 An electronic timer characterized in that, in addition to the timer output based on the output of the electronic timer, a timer output based on the output of the sub-frequency dividers 8 to 10 can be set.