JPH0446738U - - Google Patents
Info
- Publication number
- JPH0446738U JPH0446738U JP8993790U JP8993790U JPH0446738U JP H0446738 U JPH0446738 U JP H0446738U JP 8993790 U JP8993790 U JP 8993790U JP 8993790 U JP8993790 U JP 8993790U JP H0446738 U JPH0446738 U JP H0446738U
- Authority
- JP
- Japan
- Prior art keywords
- output
- frequency
- input
- circuit
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は従来のＡＩＳクロツク発生回路を示す構成図
である。
１……ＡＩＳクロツク発生回路、２，７……位
相同期回路、３……入力断検出回路、４……発振
器、５……選択器、６……信号処理回路。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a block diagram showing a conventional AIS clock generation circuit. DESCRIPTION OF SYMBOLS 1... AIS clock generation circuit, 2, 7... Phase synchronization circuit, 3... Input loss detection circuit, 4... Oscillator, 5... Selector, 6... Signal processing circuit.
Claims (1)
変換しフイルタで平滑した後、電圧制御発振器の
出力周波数を制御して、入力周波数に出力周波数
を同期させる位相同期回路と、前記入力クロツク
の断状態を検出しアラーム信号を送出する入力断
検出回路と、出力クロツクを発生する発振器と、
通常では前記位相同期回路の出力を選択し前記ア
ラーム信号を受信したときには前記発振器の出力
を選択し出力する選択器とを備えたことを特徴と
するＡＩＳクロツク発生回路。 A phase synchronization circuit that converts the phase comparison result of the input and output clocks into a voltage and smoothes it with a filter, then controls the output frequency of the voltage controlled oscillator to synchronize the output frequency with the input frequency, and a phase synchronization circuit that synchronizes the output frequency with the input frequency; An input disconnection detection circuit that detects and sends out an alarm signal, an oscillator that generates an output clock,
An AIS clock generation circuit comprising: a selector which normally selects the output of the phase locked circuit and selects and outputs the output of the oscillator when the alarm signal is received.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8993790U JPH0446738U (en) | 1990-08-28 | 1990-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8993790U JPH0446738U (en) | 1990-08-28 | 1990-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0446738U true JPH0446738U (en) | 1992-04-21 |
Family
ID=31824278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8993790U Pending JPH0446738U (en) | 1990-08-28 | 1990-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0446738U (en) |
-
1990
- 1990-08-28 JP JP8993790U patent/JPH0446738U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0218406A3 (en) | Sampling clock generation circuit | |
| JPH0446738U (en) | ||
| JPH0730422A (en) | Sampling clock generation circuit | |
| JPS633644U (en) | ||
| JPS62125029U (en) | ||
| JPH0170434U (en) | ||
| JPH02111936U (en) | ||
| JPH0344380U (en) | ||
| JPH0478618U (en) | ||
| JPH03103636U (en) | ||
| JPS6412691A (en) | Video signal sampling circuit | |
| JPS62186533U (en) | ||
| JPH05300008A (en) | Pll circuit | |
| JPS6168532U (en) | ||
| JPH01153776U (en) | ||
| JPH03130672U (en) | ||
| JPH01151671U (en) | ||
| JPS61168727U (en) | ||
| JPH0390532U (en) | ||
| JPS63125471U (en) | ||
| JPH0251408U (en) | ||
| JPH02138963U (en) | ||
| JPS63111075U (en) | ||
| JPH02134781U (en) | ||
| JPS6352316U (en) |