JPH044681A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To decrease number of amplifier means and to reduce both a resistive component and a capacitive component of the amplifier means by connecting plural storage means to one control electrode of the amplifier means in common via each transfer element. CONSTITUTION:A signal subjected to photoelectric conversion by photo diodes D1, D2 is transferred to a base of a bipolar transistor(TR) 1 via a transfer element M3. Base regions of bipolar TRs 1, 2, 3 are reset by making pMOS TRs Mc1-Mc6 in the vertical direction all conductive prior to transfer of a picture element signal. Nearly ten reset terminals are to be provided to one vertical output line VL. Since one bipolar TR is provided to two picture elements and number of bipolar TRs connecting to a vertical output line is decreased to nearly a half, the resistive component and the capacitive component are reduced and a margin is caused in the drive capability of the bipolar TRs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photoelectric conversion device aimed at reducing sensor noise.

[Prior Art] Amplification type sensors are preferably used for sensors used in solid-state imaging devices and the like in order to increase the output signal level.

Amplified sensors include MOS, SIT, and FET types.

It is composed of transistors such as bipolar type,
The charges accumulated in these control electrodes are charge amplified or current amplified and outputted from the main electrode. For example, Japanese Patent Publication No. 55-28456 discloses an example of an amplification type sensor. One of the problems with such amplified sensors is that the sensor noise is large.

Sensor noise generally includes fixed pattern noise (hereinafter referred to as FPN) that appears in a fixed manner, and random noise that is incorporated into the control electrode when the control electrode is reset (noise whose amplitude changes each time it is reset).

Since FPN appears fixedly in sensor noise, it can be completely removed by subtracting the dark output of the sensor from the optical signal output of the sensor. Note that the dark output can be obtained by setting the accumulation time to almost zero, that is, by reading out the sensor immediately after resetting it.

On the other hand, in order to remove random noise introduced into the control electrode, the sensor output (optical signal) after accumulation may be subtracted from the sensor output (sensor noise) immediately after accumulation starts.

As a photoelectric conversion device capable of such subtraction processing, the present inventor has already proposed the following photoelectric conversion device in Japanese Patent Application No. 1-301819.

FIG. 5 is a circuit diagram of the photoelectric conversion device disclosed in the above-mentioned Japanese Patent Application No. 1-301819.

FIG. 6 is a schematic plan view of one pixel of the photoelectric conversion device.

In the description of the circuit configuration, parts common to the embodiments of the photoelectric conversion device of the present invention to be described later will be denoted by the same reference numerals and the description thereof will be omitted, except for the parts necessary for the description.

As shown in Figures 5 and 6, Japanese Patent Application No. 1-30181
The pixel of the photoelectric conversion device No. 9 includes a photodiode D, which is an accumulation means for accumulating photo-excited charges, a capacitor C68,
It is composed of an amplification transistor Tr and a transfer element Ms for controlling the transfer of charges generated in the photoelectric conversion section of the photodiode D to the base, which is a control electrode of the amplification transistor Tr.

A photoelectric conversion device having such a configuration makes it possible to independently read sensor noise regardless of the operation of the photodiode D by providing a transfer element Ms between the photodiode D and the amplification transistor Tr. and
It is possible to remove not only the FPN but also the dark current component of the amplification transistor Tr and random noise.

Further, before transferring the charge accumulated in the photodiode D to the amplification transistor Tr, a reset means Mc is provided for resetting the base of the amplification transistor Tr, and after resetting, the output of the amplification transistor Tr is reset. By reading out the output of the amplification transistor Tr as a second signal after making the transfer element Ms conductive and transferring the charge of the photodiode D to the base of the amplification transistor Tr,
By removing the dark current component of the amplification transistor Tr before transferring photocharges and setting the base potential of the amplification transistor Tr lower than the accumulated potential of the photodiode D, the photoelectric charge is transferred from the photodiode D to the amplification transistor Tr. This makes it possible to completely transfer photocharges.

Furthermore, each amplification transistor T adjacent in the sub-scanning direction
By providing a reset means Me between the bases of r and resetting the base of the amplification transistor Tr by the reset means Me, it is possible to reset pixels arranged in the sub-scanning direction simultaneously with the main scanning direction, thereby reducing smear. It has an effect.

Note that smear is caused by excessively strong light irradiation, etc., so when reading out a signal corresponding to the accumulated charge, the potential of the control electrode of the unselected amplification means increases, and an output appears from the amplification means. It refers to a phenomenon.

The above smear can be reduced by using the control electrode of the selected amplifying transistor Tr as well as the control electrode of the unselected amplifying transistor Tr before reading out the signal corresponding to the accumulated charge from the selected amplifying means. Since the control electrode can also be reset, no output will appear from the unselected amplification transistor Tr (
Because it will be.

[Problems to be Solved by the Invention] However, when the photoelectric conversion device of the above-mentioned Japanese Patent Application No. 1-301819 is applied to a gate isolation type photoelectric conversion device in which the element isolation region has an insulated gate transistor structure, the number of pixels increases. Since the reset time becomes longer as the number increases, improvements have been desired.

The reason why the reset time is longer is that, as shown in FIGS. 5 and 6, since the reset means Me are arranged in series, the series resistance (ON resistance component of the reset means Mc, base resistance component of the amplification transistor Tr) etc.) and capacity (
This is because the base capacitance of the amplifying transistor Tr, the parasitic capacitance of the emitter, etc. becomes large, and the time constant becomes long.

Examples of applications where shortening the reset time are desired include:
There are the following:

When operating an area sensor (a plurality of photoelectric conversion elements arranged two-dimensionally) used in solid-state imaging devices etc. in synchronization with a television, reset is performed within one horizontal planking (IHBLK) or - A case may be considered in which the horizontal scanning period is used. In this case, in the case of a photoelectric conversion device in which the element isolation region has an insulated gate transistor structure as described above, it is necessary to perform reset within the IHBLK period.

However, if there is an application in which it is desired to read out pixel signals of two horizontal pixel columns independently within one horizontal scanning period, Japanese Patent Application No. 1-3
The photoelectric conversion device of No. 01819 has a long reset period, so it is difficult to deal with this problem.

When it is desired to obtain luminance signals and color signals with high vertical resolution using a color sensor, it is necessary to independently output pixel signals of two horizontal pixel columns, so a photoelectric conversion device that can be used for such purposes has been desired.

[Means for Solving the Problems] The photoelectric conversion device of the present invention includes a pixel whose constituent elements are an accumulation means for accumulating photo-excited charges and a transfer element that controls the transfer of the charges accumulated in the accumulation means. A photoelectric conversion device comprising a plurality of storage means commonly connected to a control electrode via respective transfer elements, an amplification means for amplifying and outputting the electric charge of the control electrode, and an amplification means provided on the control electrode. a first readout means for resetting the control electrode by the reset means and reading out the output of the amplification means as a first signal; a transfer means for transferring the charge to a control electrode; a second readout means for reading out the output of the amplification means as a second signal after transferring the charge; and a subtraction process for subtracting the first signal and the second signal. It is characterized by comprising a processing means, and.

[Function] The present invention reduces the number of amplification means by commonly connecting a plurality of storage means to one control electrode of the amplification means through their respective transfer elements, and reduces the resistance component and capacitance component due to the amplification means. This is to make the size smaller.

Further, the present invention provides a reset terminal of the reset means for each of the plurality of amplification means, thereby reducing an additive increase in resistance and capacitance caused by series connection of the reset means.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is an equivalent circuit diagram of an embodiment of the photoelectric conversion device of the present invention.

The pixels of the photoelectric conversion device of this embodiment are arranged in a matrix of m rows and n columns, but in FIG. 1, only large pixels S, to S6 in the first column are shown for simplicity. shall be indicated.

As shown in FIG. 1, each pixel S, to S6 is used to control the transfer of charges generated in the photoelectric conversion section of photodiode D, capacitor C8X, and photodiode D, which are storage means for storing photoexcited charges. It is composed of transfer elements Ms.

Two pixels in the vertical direction, pixel S1 and pixel S2. Pixel S3 and pixel S4. Pixel S and pixel s6 are bipolar transistors T r + and T r 2HTr, respectively.
connected to i.

Bipolar transistor Tr, in the vertical direction.

Two pMOs between Tri) transistors MC2 and MC8
bipolar transistors 7172. Tr
i is separated by two pMOs) transistors MC4 and Mcs. Further, a pMOS transistor Mc+ is provided on one side of the bipolar transistor Tr+.

Bipolar transistor T r++ T r2. T
The emitter terminals of rs are commonly connected to the vertical output line VL. 2 pMOs) transistor MCz 9MCs
, Me, , and Mcs are commonly connected, and the drains of the pMOS transistors MC4 and Mcs are connected to the vertical output line VL. In addition, p MO
The drain of the S transistor is connected to the vertical output line VL as necessary.

pMOS transistor Mc+ + 1llGK + M
The gates of cs l MC4+Mcs are commonly connected to a reset gate line GL. A pulse φeL is applied to this gate line.

The vertical output line ■L is connected to storage capacitors CT, CA2 via nMOS transistors I + MT2 controlled by pulses φA, , φT2. Storage capacity C
Sensor noise and signals are accumulated in A1 and C70, respectively, and the sensor noise output (5o
ut) and is outputted to the horizontal output line as a signal output (Nout), subjected to subtraction processing by a subtraction processing circuit (not shown), and outputted to the horizontal common output line SL. Horizontal common output line SL is reset by a MOS transistor controlled by pulse φHe.

The vertical output line VL is controlled by the pulse φve.
It is reset by the OS transistor Mv, and it is possible to remove residual charges in the storage capacitors CTI and CT□ and to perform transient refreshing of bipolar transistors Tr+ to Tr3, which will be described later.

FIG. 2 is a schematic plan view of the photoelectric conversion device of the present invention.

Similar to FIG. 1, only the six pixels 81 to S6 in the first column are shown for the sake of simplicity.

In the figure, D1 to D6 are photodiodes D of each pixel, which are storage means for accumulating photo-excited charges, and the signals photoelectrically converted by the photodiodes D and D2 are transferred to the transfer element M, (in the figure , dashed line region M,) and is transferred to the base of the bipolar transistor Tr+. The capacitor C3X (indicated by the broken line in the figure) is connected to the control electrode (
gate electrode). Similarly, the signals photoelectrically converted by the photodiodes D and D4 are transferred to the base of the bipolar transistor Tr2, and the signals photoelectrically converted by the photodiodes Da and D8 are transferred to the base of the bipolar transistor Tra.

Note that this bipolar transistor Tr+I Tr2,
The base region of Tri is reset by turning on all the vertical PMOS transistors Mc+ to 1IlC6 before transferring the pixel signal. In the figure, B and E respectively indicate the base and emitter of the bipolar transistor Tr (the same applies to other pixels), and RC indicates the contact portion of the reset terminal for setting the reset potential.

The reset terminal is used to reduce the reset time constant and is provided between the PMOS transistors.Normally, this reset terminal is used to reduce the reset time constant.
It is sufficient to provide about 0 pieces. Since the reset voltage (here GND) is supplied by these 10 reset terminals,
Vertical series resistance and parasitic capacitance are each approximately 1/1
The reset time, which conventionally required an IH period, becomes approximately 1/100 times faster, making it possible to reset at a high speed.

In addition, since one bipolar transistor is provided for every two pixels, the number of bipolar transistors connected to the vertical output line is reduced by about half, which reduces the resistance and capacitance components (mainly due to emitter parasitics). (The load capacitance due to capacitance becomes smaller), and the drive capacity of the bipolar transistor becomes more leeway.

FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion device.

Note that when reading out pixel signals of two horizontal pixel columns, the operation described below may be performed for the two pixel columns. In the following description, only the operation of the pixel S will be described, but the operations of the other pixels are similar.

First, in period T, pulse φVC is set to high level,
When pulse φeL is set to low level, MOS transistor Mv, pMOS transistor Mc'+ ~ Mcs
turns on, and the vertical output line VL and bipolar transistors T rl+ T r2 . The base of T rs is reset.

Next, in period T2, while keeping the MOS transistor Mv in the ON state, if the pulse φ8 is changed from the middle level to the high level and the pulse φ11 is changed to the high level, n
The MOS transistor MTI is turned on and the storage capacitor CTl is reset, and the base potential of the bipolar transistor Tr+ rises, and the charge remaining in the base is discharged (this is called transient refresh).

Next, in period T3, when the pulse φvc is set to a low level while keeping the pulse φ8 at a high level and the pulse φTl at a high level, the bipolar transistor T r +
The offset voltage of is read out and transferred to the storage capacitor Ct+ as sensor noise.

After that, the pulse φvc is set to high level and the pulse φT2 is set to high level, and the MOS transistors Mv and nMOS
The storage capacitor C1° is reset by turning on the transistor MT2. Next, in period T4, when the pulse φ3 is changed from the middle level to the low level, the transfer element MS is turned on, and the photoelectrically converted signal from the photodiode D is transferred. is transferred to the base of bipolar transistor T r +.

Next, in period T5, the pulse φ6 changes from low level to high level, and the pulse is turned off. When set to high level, a signal corresponding to the charge transferred to the base of the bipolar transistor Tr+ is read out to the vertical output line VL, and the signal is transferred to the storage capacitor CT□.

Thereafter, in period T6, when the pulse φH1 is set to high level, the storage capacitor CT1. The sensor noise and signal accumulated in the C part 2 are outputted, subjected to subtraction processing by a subtraction processing circuit (not shown), and outputted as a noise correction signal.

Note that in the photoelectric conversion device described above, one amplification means (bipolar transistor) is provided for two vertical pixels, but one amplification means may be provided for pixels on three sides.

In addition, in the photoelectric conversion device described above, the area sensor was described, but even in the line sensor, if one amplification means is provided for each plurality of pixels, there will be a margin in the pattern design of the amplification means, making it suitable for miniaturization. A line sensor can be provided.

FIG. 4 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied.

In the figure, an image sensor 201 in which optical sensors are arranged in an area is subjected to television scanning by a vertical scanning section 202 and a horizontal scanning section 203.

The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 and output as a standard television signal.

Drive pulse φ for vertical and horizontal scanning units 202 and 203
MB+ φHI+ φH2, φV8+ φVl+
φ9□, etc. are supplied by the driver 205. The driver 205 is also limited by the controller 206.

[Effects of the Invention] As explained in detail above, according to the photoelectric conversion device of the present invention, a plurality of storage means are commonly connected to one control electrode of the amplification means via their respective transfer elements, thereby achieving amplification. By reducing the number of means, it is possible to reduce the resistance and capacitance components of the amplification means (if the amplification means is a bipolar transistor, it is possible to reduce the parasitic capacitance of the emitter in particular).
It is possible to reduce the degree of signal destruction, it is possible to perform a high-speed reset, and it is possible to read out pixel signals of multiple horizontal pixel columns independently. In addition to this effect, by providing a reset terminal of the reset means for each of the plurality of amplification means, it is possible to reduce the additive increase in resistance and capacitance caused by series connection of the reset means, and to perform the reset at a higher speed. .

Note that the number of contacts for reset potential is very small (
This will improve its retention.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of an embodiment of the photoelectric conversion device of the present invention. FIG. 2 is a schematic plan view of an embodiment of the photoelectric conversion device of the present invention. FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion device. FIG. 4 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. FIG. 5 is a circuit diagram of a photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819. FIG. 6 is a schematic plan view of one pixel of the photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819. S, -S,: pixel, D=photo diode, Cox:
Capacity, Ms: Transfer element, Tr++ Tr2. Tra:
Bipolar transistor, Mc+, Mci, Mcs, M
c4゜MCs: pMO3) transistor, SL: horizontal common output line, ■L: vertical output line, GL two gate line, MT
l +MT, : MOS transistor, CTI
, C70: Storage capacity, M, , M, , Mv: MO
S transistor. Agent Patent Attorney Sekihei Yamashita Figure 2 Figure 3 1→→ ←--- Tt Nono T4 T5 γ6 Figure 4 Figure 5 Figure 6

Claims (3)

[Claims] (1) A photoelectric conversion device comprising a plurality of pixels whose constituent elements are an accumulation means for accumulating photo-excited charges and a transfer element that controls transfer of the charges accumulated in the accumulation means, the plurality of accumulation means are commonly connected to the control electrode via the respective transfer elements, an amplifying means for amplifying and outputting the charge of the control electrode; a reset means provided on the control electrode; and a reset means for controlling the control electrode by the reset means. a first readout means for resetting and reading out the output of the amplification means as a first signal; a transfer means for making the transfer element conductive and transferring the charge of the storage means to the control electrode; A photoelectric conversion device comprising: second readout means for reading out the output of the amplification means as a second signal; and subtraction processing means for performing subtraction processing between the first signal and the second signal. (2) The photoelectric conversion device according to claim 1, wherein the reset means is provided between control electrodes of amplification means adjacent in the sub-scanning direction. (3) The photoelectric conversion device according to claim 2, wherein a reset terminal of the reset means is provided for each of the plurality of amplification means.