JPH044752B2 - - Google Patents

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Publication number
JPH044752B2
JPH044752B2 JP146486A JP146486A JPH044752B2 JP H044752 B2 JPH044752 B2 JP H044752B2 JP 146486 A JP146486 A JP 146486A JP 146486 A JP146486 A JP 146486A JP H044752 B2 JPH044752 B2 JP H044752B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
active layer
stacked semiconductor
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP146486A
Other languages
Japanese (ja)
Other versions
JPS62160737A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP146486A priority Critical patent/JPS62160737A/en
Publication of JPS62160737A publication Critical patent/JPS62160737A/en
Publication of JPH044752B2 publication Critical patent/JPH044752B2/ja
Granted legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、積層型半導体装置の積層化構造に
関するものであり、特に積層化プロセスにおいて
発生するストレス(熱応力)を回避する方法に関
するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a stacked structure of a stacked semiconductor device, and particularly relates to a method for avoiding stress (thermal stress) generated in the stacking process. be.

〔従来の技術〕[Conventional technology]

第3図は従来の積層型半導体装置のSOI
(Silicon on Insulator)構造を示す断面図であ
り、第n番目の活性層1の上に非電導物質を第n
番目の層間絶縁層3として形成し、さらにその上
に第(n+1)番目の活性層2を形成することに
よりSOIの積層構造を実現している。
Figure 3 shows the SOI of a conventional stacked semiconductor device.
(Silicon on Insulator) structure, in which a non-conductive material is placed on the nth active layer 1.
An SOI layered structure is realized by forming the first interlayer insulating layer 3 and further forming the (n+1)th active layer 2 thereon.

第3図に示す積層型半導体装置は、活性層1,
2中に、FET(Field Effect Transistor)、ある
いはその他の抵抗やコンデンサなどの電気部品を
使つて回路を形成し、さらに上下の回路を層間絶
縁膜3を介して配線し、3次元に配置された回路
を形成したものである。上記従来技術による積層
型半導体装置においては、活性層2を形成するた
めに、レーザビームもしくはエレクトロンビーム
を利用して、堆積したポリシリコンの再結晶化を
行つている。
The stacked semiconductor device shown in FIG.
2, a circuit is formed using FETs (Field Effect Transistors) or other electric components such as resistors and capacitors, and the upper and lower circuits are further wired through an interlayer insulating film 3, and the circuit is arranged three-dimensionally. A circuit is formed. In the stacked semiconductor device according to the prior art described above, in order to form the active layer 2, the deposited polysilicon is recrystallized using a laser beam or an electron beam.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の積層型半導体装置は、第3図のように構
成され、層間絶縁膜3の上に活性層2を形成して
いるので、この活性層2の形成において堆積した
ポリシリコンをレーザビームやエレクトロンビー
ムで再結晶化することが必要であり、この時に上
記両層2,3の熱膨張係数の差でストレス(熱応
力)が発生し、基板の反りが起るなどの問題点が
あつた。
A conventional stacked semiconductor device is constructed as shown in FIG. 3, and an active layer 2 is formed on an interlayer insulating film 3. During the formation of this active layer 2, the deposited polysilicon is exposed to a laser beam or an electron beam. It is necessary to perform recrystallization using a beam, and at this time stress (thermal stress) is generated due to the difference in the thermal expansion coefficients of the two layers 2 and 3, causing problems such as warping of the substrate.

この発明は上記のような問題点を解消するため
にされたもので、基板の反りを回避できる積層型
半導体装置を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a stacked semiconductor device that can avoid warping of the substrate.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る積層型半導体装置は、層間絶縁
層とその上の活性層との間に、薄いシリコン層と
薄い酸化シリコン層もしくは窒化シリコン層とを
交互に複数層重ねてなる薄膜多層構造のバツフア
層を組み込むようにしたものである。
A stacked semiconductor device according to the present invention has a buffer of a thin film multilayer structure in which a plurality of thin silicon layers and thin silicon oxide layers or silicon nitride layers are alternately stacked between an interlayer insulating layer and an active layer thereon. It is designed to incorporate layers.

〔作用〕[Effect]

この発明においては、上記バツフア層が、上下
の活性層と層間絶縁層との熱膨張係数の違いによ
り再結晶化時に発生するストレス(熱応力)を吸
収し、これにより基板の反りの発生を回避すると
ともに、上記活性層の再結晶化時における結晶性
を向上させる。
In this invention, the buffer layer absorbs the stress (thermal stress) that occurs during recrystallization due to the difference in thermal expansion coefficient between the upper and lower active layers and the interlayer insulating layer, thereby avoiding the occurrence of warping of the substrate. At the same time, the crystallinity of the active layer during recrystallization is improved.

〔実施例〕〔Example〕

以下、この発明の一実施例を図つていて説明す
る。
Hereinafter, one embodiment of the present invention will be illustrated and explained.

第1図は本発明の一実施例による積層型半導体
装置を示し、図において、1は積層型半導体装置
における第n番目の活性層、2は第(n+1)番
目の活性層、3は第n番目の活性層1と第(n+
1)番目の活性層(2)とを分離する層間絶縁層であ
り、4はバツフア層である。
FIG. 1 shows a stacked semiconductor device according to an embodiment of the present invention, in which 1 is the nth active layer in the stacked semiconductor device, 2 is the (n+1)th active layer, and 3 is the nth active layer. active layer 1 and (n+
1) This is an interlayer insulating layer that separates the active layer (2), and 4 is a buffer layer.

第2図にバツフア層4の拡大図を示す。このバ
ツフア層4は膜厚10〜100Åの薄いシリコン層4
aと同じく膜厚10〜100Åの薄い酸化シリコン層
(もしくは窒化シリコン層)4bとが交互に積み
重ねられた薄膜多層構造となつている。ここで上
記膜厚の下限10Åは1原子層の厚みは5Åでほぼ
2〜3原子層の厚みということであり、上限100
Åはこれ以上厚いと後述する熱ストレス吸収の効
果を発揮できないからである。
FIG. 2 shows an enlarged view of the buffer layer 4. This buffer layer 4 is a thin silicon layer 4 with a thickness of 10 to 100 Å.
Like a, it has a thin film multilayer structure in which thin silicon oxide layers (or silicon nitride layers) 4b having a thickness of 10 to 100 Å are stacked alternately. Here, the lower limit of the above film thickness of 10 Å means that the thickness of one atomic layer is 5 Å, which is approximately 2 to 3 atomic layers, and the upper limit of 100 Å.
This is because if Å is thicker than this, the effect of absorbing heat stress, which will be described later, cannot be exhibited.

第1図に示すような積層型半導体装置を形成す
るプロセスにおいては、活性層2を形成するた
め、堆積したポリシリコンの再結晶化プロセスを
行なうが、本実施例では上記ポリシリコンを堆積
し、再結晶化プロセスを行なう前に、バツフア層
4を形成するようにしており、これにより、活性
層2の再結晶化プロセスにおいて発生する熱応力
を該バツフア層4により吸収し、基板の反りを回
避することができる。またさらにこの基板の反り
を回避できることによつてその後のウエハプロセ
スの精度の向上も期待できる。
In the process of forming a stacked semiconductor device as shown in FIG. 1, the deposited polysilicon is recrystallized in order to form the active layer 2. In this example, the polysilicon is deposited, Before performing the recrystallization process, a buffer layer 4 is formed, so that the thermal stress generated during the recrystallization process of the active layer 2 is absorbed by the buffer layer 4, thereby avoiding warpage of the substrate. can do. Furthermore, by being able to avoid warping of the substrate, it can be expected that the precision of subsequent wafer processes will be improved.

なお、上記実施例では薄膜多層構造のバツフア
層としては、シリコン層と酸化シリコン(もしく
は窒化シリコン)層との重ね合わせによるものを
用いたが、これはシリコン層、酸化シリコン層、
窒化シリコン層、PSGなど3種類以上の物質を
積層化し、バツフア層にすることも可能である。
Note that in the above embodiments, the buffer layer of the thin film multilayer structure was formed by overlapping a silicon layer and a silicon oxide (or silicon nitride) layer;
It is also possible to form a buffer layer by laminating three or more types of materials such as a silicon nitride layer and PSG.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、バツフア層
を層間絶縁膜と活性層との間に形成するようにし
たので、熱応力による基板の反りを回避でき、活
性層として質の良いシリコン層を得られる効果が
ある。また基板の反りを回避できるために、その
後のウエハプロセスの精度の向上も期待できる。
As described above, according to the present invention, since the buffer layer is formed between the interlayer insulating film and the active layer, warping of the substrate due to thermal stress can be avoided, and a high-quality silicon layer can be used as the active layer. There are benefits to be gained. Furthermore, since warpage of the substrate can be avoided, it is expected that the accuracy of subsequent wafer processes will be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による積層型半導
体装置を示す断面図、第2図は第1図中のバツフ
ア層の構造を示す断面図、第3図は従来の積層型
半導体装置を示す断面図である。 1…第n番目の活性層、2…第(n+1)番目
の活性層、3…第n番目の層間絶縁層、4…バツ
フア層。なお図中同一符号は同一又は相当部分を
示す。
FIG. 1 is a sectional view showing a stacked semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing the structure of the buffer layer in FIG. 1, and FIG. 3 is a conventional stacked semiconductor device. FIG. 1... nth active layer, 2... (n+1)th active layer, 3... nth interlayer insulating layer, 4... buffer layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】 1 SOI層を有する積層型半導体装置において、 活性層であるシリコン層と層間絶縁膜である酸
化シリコン層との間に、薄いシリコン層と薄い酸
化シリコン層もしくは窒化シリコン層とを交互に
複数層積重ねてなる薄膜多層構造のバツフア層を
有することを特徴とする積層型半導体装置。
[Claims] 1. In a stacked semiconductor device having an SOI layer, a thin silicon layer and a thin silicon oxide layer or a silicon nitride layer are provided between a silicon layer as an active layer and a silicon oxide layer as an interlayer insulating film. 1. A stacked semiconductor device comprising a buffer layer having a thin film multilayer structure formed by alternately stacking a plurality of layers.
JP146486A 1986-01-09 1986-01-09 Laminated type semiconductor device Granted JPS62160737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP146486A JPS62160737A (en) 1986-01-09 1986-01-09 Laminated type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP146486A JPS62160737A (en) 1986-01-09 1986-01-09 Laminated type semiconductor device

Publications (2)

Publication Number Publication Date
JPS62160737A JPS62160737A (en) 1987-07-16
JPH044752B2 true JPH044752B2 (en) 1992-01-29

Family

ID=11502182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP146486A Granted JPS62160737A (en) 1986-01-09 1986-01-09 Laminated type semiconductor device

Country Status (1)

Country Link
JP (1) JPS62160737A (en)

Also Published As

Publication number Publication date
JPS62160737A (en) 1987-07-16

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