JPH0447558A - Dubbing device - Google Patents

Abstract

PURPOSE:To perform the after-recording processing of sound by providing a means to switch a digital audio signal of N bits comprising a digital signal of N+M bits with another digital audio signal of N bits. CONSTITUTION:The digital signal DSm supplied from a digital audio tape recorder (DAT) 301 via a change-over switch 303 is supplied to the fixed terminal (a) of the change-over switch 341 of an after-recording device 304, and audio signals SaL and SaR on right and left channels for switching are supplied to a signal processing circuit 342. A timing generation circuit 343 goes to a low level corresponding to the video signal DSv of the digital signal DSm based on clocks BCK, LRCK, and also, it goes to a high level corresponding to an audio signal DSa', then, a word clock WCK is generated, and it is supplied to the changeover switch 341. Thereby, the digital signal DSs in which the part of the audio signal DSa' of the digital signal DSm is switched is outputted, thereby, the after-recording processing of the sound is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an apparatus for dubbing a digital signal obtained by combining a digital audio signal and a digital video first word.

[Prior art] The current digital audio tape recorder (hereinafter referred to as "D")
(referred to as "AT") is designed to record and reproduce only audio signals.

However, since it would be very convenient to record and play back not only audio signals but also other signals, such as video signals for still images, the applicant first synthesized digital audio signals and digital video signals. , proposed simultaneous recording and playback.

[Problems to be Solved by the Invention] By the way, it would be even more convenient if audio dubbing could be performed when the above-mentioned synthesized digital signal reproduced by one DAT is recorded and dubbed by another DAT.

Therefore, in the present invention, it is possible to perform audio dubbing processing.

[Means for Solving the Problem] The second invention combines an N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal to record an N+M-bit digital signal. In a dubbing device for recording the N+M-bit digital signal reproduced from one recording medium, which is reproduced from a recording medium, onto another recording medium, an N-bit digital audio signal constituting the N+M-bit digital signal reproduced from a negative recording medium. It is provided with means for replacing the N-bit digital audio signal with another N-bit digital audio signal.

[Function] In the above configuration, during dubbing, the N-bit digital audio signal constituting the N+M-bit digital signal can be replaced. This enables voice dubbing processing.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

In this example, the analog audio signal is one sample l
O-bit Digital Oday No. 18 DSa [A9~
The digital audio signal DSa' [
A? '~AO'] (shown in FIG. 1B).

Further, the analog video signal is converted into a digital audio first word DSv[V7 to vO] of 8 bits per sample (as shown in FIG. 1C).

The second diagram shows the format of the digital signal DS recorded and reproduced in this example.

Of the 16-bit data D15-DO, the upper 8 bits contain the digital audio signal DSa'[A7'-A
O'] is arranged, and a digital video signal DSv[V7 to VO] is arranged in the lower 8 bits.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic spatula F (not shown) provided on the DAT, is recorded on a magnetic tape, and is reproduced from the magnetic tape.

As will be described later, the DAT sequentially records both the left (L) channel and right (R) channel digital audio signals DSa sampled at the clock fs. Therefore, each sample data of the digital video signal DSv is mixed with the digital audio signal DSa and recorded at the same time as clock 2fs.

48kHz as audio sampling clock fs
When using , the video sampling clock is 4fsc
(In the case of NTSC system, fsc is 3.58MHz), there is a frequency of 149 MHz between the video sampling clock 4fsc and the above-mentioned clock 2fs.
There is a difference of about twice that. In other words, the digital video signal DSv sampled at a period of 1/4 f sc
Each sample data is 1/2fs (1/4fsc
49 times)).

Therefore, since one frame period leap is 1/3o second,
It will take approximately 4.96 seconds to record one frame (odd and even fields) of the video signal. Moreover, as will be described later, since an identification code ID is added to the video signal, it takes about 5 seconds to finally record one frame of the video signal.

FIG. 3 is a diagram showing the data structure. In other words, immediately before the video signal of each of the odd (ODD) and even (EVEN) fields that make up one screen, there is a start code S-rD that indicates the start of data, and a start code that indicates whether it is an odd or even field. Mote code MD-ID
, A last start code LS/ID is added to distinguish the identification code from the data. Further, a stop code F'E•ID indicating the end of data is added immediately after the video signal of each field.

For example, the start code S-ID is composed of 8-bit data with only the least significant bit being "1", and the stop code E-ID is composed of 8-bit data with all bits being "0".

11th! 1 is an example of a signal processing device for forming a digital signal DS having a format as shown in the second figure and recording and reproducing it on a DAT with a data structure as shown in FIG.

First, a signal processing system for audio signals will be explained.

Left and right channel audio signals SaL and SaR supplied to audio in terminals 8L and 8R are amplifier 9L.
, amplified by 9R, noise reduction circuit 10L
, IOR removes noise, and low-pass filter IIL
, IIR band-limited.

Then, it is supplied to the A/D converters 12L and 12R.
Bit digital audio signals DSaL, DSaR
is converted to An audio sampling clock fs (48 kHz) is supplied to the A/D conversion @12L and 12R.

Digital audio signals DSaLS and DSaR output from the A/D converters 12L and 12R are supplied to Lll and RIM of the changeover switch 13, respectively.

A clock LRCK with a frequency of 48kHz and a duty of 50% is supplied to this changeover switch 13, and a clock LRCK with a frequency of 48kHz and a duty of 50% is supplied,
It is alternately switched to Lll and R111 every cycle U4 of z.

The digital audio signal DSa output from the changeover switch 13 is supplied to a compression circuit #4, where it is converted from a 10-bit signal to a 1-sample 8-bit signal.

The digital audio signal DSa' converted into an 8-bit signal by the compression circuit 14 is supplied to a mixing means (adder) 20 constituting the mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later.

The mixed digital signal DS (shown in the second diagram) is then supplied to the digital out processing surface M22,
It is converted into a digital signal in a form compliant with the AT audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a pit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head (not shown) of the DAT via the digital out terminal 24 and recorded.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a digital-in terminal 32, and subjected to digital-in processing. For example, a PLL @ path (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the next-stage separation means 36 outputs the digital audio signal DSa' (shown in FIG. 2B) and the digital The video signal DSv (shown in C of the same figure) is separated and output.

The 8-bit digital audio signal DSa' separated by the separating means 36 every 1/96 kHz is supplied to the decompression circuit 38. In this expansion circuit 38,
The digital audio signal DSa, which has been made into a 10-bit signal by the decompression circuit 38, undergoes processing opposite to that of the compression circuit 14, and the 1-sample 8-bit signal is returned to the 1-sample 10-bit signal. 39 movable terminals. A clock LRCK is supplied to this changeover switch 39, and Ll
It is alternately switched to l and Rm.

In other words, the fixed terminals on the Lll and R sides of the changeover switch 39 are connected to the left and right channel digital audio DSaL and DSaR with wIM of 1/48kHz, respectively.
is obtained.

The digital audio DSaL and DSaR output from the changeover switch 39 are output from the D/A converters 4OL and 40.
R and is converted into an analog signal.

(7) A/D conversion! 4OL, 4OR, and audio sampling clock fs are supplied.

The audio signals S aL and S aR output from the D/A converters 40L and 4OR are passed through a low-pass filter 41.
The band is limited by L and 41R, and the noise reduction circuit 4
After the noise is removed by 2L and 42R, it is further amplified by amplifiers 43L and 43R and sent to audio out terminal 4.
Output to 4L and 44H.

Next, a signal processing system for video signals will be explained.

The still image video signal Sv supplied to the video in terminal 50 is amplified by an amplifier 52 and then sent to an A/D converter 5.
4 and is converted into a digital signal of 8 hits per sample. This A/D conversion W54 has 4 f sc
(f sc is the subcarrier frequency, 3°58M
Hz) sampling clock is used.

The digital video signal DSν output from the A/D converter 54 is supplied to a fixed terminal on the a side of a changeover switch 56 that switches between a human input signal and a reproduction signal. The output signal of this changeover switch 56 is supplied to memories 62 and 64 constituting the memory means 60 as a write signal.

The memories 62 and 64 each have a storage capacity for one frame. Writing and reading of these memories 62 and 64 are controlled by supplying control signals to memory control circuits 70 and 72 from a controller 100 having a CPU.

The video signal Sv supplied to the terminal 50 is supplied to the subcarrier extraction circuit 110 via the amplifier 52, and the subcarrier fsc extracted by this extraction circuit 110 is supplied to the controller 100. Further, the digital video signal DSv output from the A/D converter 54 is supplied to a vertical simultaneous separation circuit 112, and the vertical synchronization signal separated by this separation circuit 112 is supplied to the controller 100. Control signals are supplied to the memory control circuits 70 and 72 based on the subcarrier fsc, the vertical synchronization signal, and the bit clock BCK.

In this case, during recording, writing to the memories 62 and 64 is performed at a rate of 4 fsc, and
The reading is performed with a clock of 2fs to one memory and 4fs to the other memory.
This is done using the sc clock. That is, one memory functions as a time axis compression means for the digital video signal DSv because it combines the digital video signal DSv with the above-mentioned digital audio signal DSa.

Also, during playback, writing to the memories 62 and 64 is performed using a clock with a frequency of 2fs, and
The reading is performed with a clock of 4 fsc. In other words, the memories 62 and 64 function as time axis expansion means for the digital video signal DSv.

The signal read from the memory 62 is transferred to the selector switch 66.
．． The signal supplied to the fixed terminal of ELL on the 6th and read out from the memory 64 is supplied to the f-side fixed terminal of the changeover switch 66, 68. These changeover switches 66.68
The switching is controlled by the controller 100.

The digital video signal DSv output from the changeover switch 68 is supplied to a sync bit shift encoder 76, where a sync bit shift process is performed.

Originally, a video signal is A/D converted into 8 bits, so its sync bits are digital data in which all bits are "0". However, since the identification code ID is assigned to bits that do not affect the image as described above, the encoder 76 shifts the sync bit by one bit so that the identification code ID and the sync bit can be distinguished. (See Figure 4).

The digital video signal DSv, on which the sync bits have been shifted by the encoder 76, is supplied to the adder 7, and the adder 7 adds an identification code F'ID (see FIG. 3). 80 is the identification code F' I
This is the generator of D.

The digital video signal DSv to which the identification code rD is added by the adder 7 is subjected to parallel/serial conversion processing in the signal processing circuit 82, and bit inversion processing is performed on the most significant bit MSB of the digital video signal DSv. This process will be described later.

The digital video signal DSv, which has been subjected to predetermined signal processing by the signal processing circuit 82, is mixed with the digital audio signal DSa' by the mixing means 20, as shown in the second diagram, and sent to DATa.

Furthermore, when reproducing the digital signal DS, the separating means 36
The digital video signal DSv that is separated is subjected to serial/parallel conversion processing in the signal processing circuit 90, and also inversion processing of the most significant bit (bi SB) of the digital video signal DSv is performed.

Then, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite manner to the recording process, and after returning to the original sync bits (see FIG. 4), the changeover switch 56
is supplied to the fixed terminal on the b side.

Switching of the changeover switch 56 is controlled by the controller 100, and it is connected to all during recording, and connected to bs during playback.

Further, the digital video signal DSν outputted from the changeover switch 66 is supplied to the gll fixed terminal of the changeover switch 102, and the A/D converter 54 is connected to the fixed terminal on the h side.
output signal is provided. This switching of the changeover switch 102 is controlled by the controller 100. In other words, when displaying a video (through image) during recording, h
g when connecting to a and displaying still images to be recorded.
connected to l. During playback, it remains connected to the g side.

The digital video signal DSv outputted from the changeover switch 102 is converted into an analog signal by the D/A converter 104, and then outputted to the video out terminal 10 via the amplifier 106. A monitor means (0, not shown) is connected to this terminal 10.

Further, the output signal of the signal processing circuit 90 is supplied to an identification code detector 94. The identification code ID detected by the detector 94 is supplied to the controller 100. Based on this identification code ID, the memory control circuit 70.72
is controlled.

During reproduction, when the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 6o, only image data is stored. At that time, in both odd and even fields, the final data is when a predetermined period of time has elapsed from the first data of the image data.
In order to detect this final data more accurately, in addition to management based on time, a stop code E-ID is detected, and when the two match, it is determined as final image data.

Then, when the writing of the final image data of the even field is completed, the writing and reading modes of the memory 62.64 are reversed, and the selector switch 66.6
8 can also be switched to the opposite side.

By the way, during the reproduction of the digital video signal DSv, the DA
When the reproduction of T is stopped, all bits of the reproduction output data supplied to the terminal 32 become "o" as shown in FIG.

Time management (count-up processing) for image data is performed in the 1st f! Since this is carried out on the signal processing device side shown in fJ, even if the reproduction of the DAT stops, the count-up processing will also stop in conjunction with this.

Therefore, one memory of the memory means 60, for example, the memory 64, remains in the read state, and all bits are
OJ data is accepted as original image data.

When a predetermined period of time has passed since the DAT stopped mode, the reproduction time for the final image data of the even field has arrived, and since all bits of the reproduction data at that time are always "o", this is set as the stop code E. - Misjudged as ID. As a result, the signal processing device considers that the final image data has arrived, and switches the changeover switch 66.6.
As the day changes, memory 64 is placed into read mode.

Then, after DAT goes into stop mode, memory 6
Since all the bits "0" data written in 4 is read out and displayed as a black image, a very unsightly image will be displayed on the monitor.

To avoid this, if the most significant bit of the image data is inverted and recorded as described above and then inverted again during playback, as shown in Figure 5, all bits of the playback output data when stopped midway will be
0'', if the re-inversion process is performed, the most significant bit MSB becomes rlJ.

As a result, the signal processing device side does not judge that the final screen data has arrived, and the memory means 60 does not perform switching control, so the previous screen is always monitored, and the above-mentioned drawbacks are eliminated. Ru.

The controller 100 also includes a shutter switch 5.
WSH1 Record switch 5WRE, Playback switch 5WPL
, Bozenuitte 5WPA, stop switch 5WST, and recording mote selection switch SWMO are connected.

When the playback switch 5WPL is turned on, it is the time of playback. As a result, the DAT is placed in a playback state, and
The changeover switch 56 is connected to the b side.

The reproduced digital video signal DSv is written into one of the memories 62 and 64 via the changeover switch 56 with a clock of 2 fs. While being written to one of the memories 62.64, the digital video signal DSv for one frame is repeatedly read out from the other memory with a clock of 4 fsc, and the digital video signal DSv for one frame is repeatedly read out from the other memory with a clock of 4
After the signal is supplied to the D/A converter 104 through 02 and converted into an analog signal, it is supplied to a monitor to display a still image.

When one field's worth of final image data is written into one memory, the write and read modes of the memories 62 and 64 are reversed, and the selector switch 66 is also switched.

As a result, the reproduced digital video signal DSν is now written to the other memory with a clock of 2 fs, and the digital video signal DSv for one frame is repeatedly read out from one memory with a clock of 4 fsc. , the resulting still image is displayed on the monitor.

Thereafter, reading and writing to and from the memories 62 and 64 are repeated as described above.

Next, when the recording switch 5WRE is turned on, it is time for recording. As a result, the DAT is placed in a recording state, and the changeover switch 56 is connected to the a side.

During this recording, the mode selection switch SWMO is
When connected to the 5lil, m1ll, and a sides, respectively, the mode becomes one-shot mode, manual mode, and auto mode.

In one-shot mode, shutter switch 5WS)
In manual mode, when l is turned on, image data for one frame is loaded into the memory, this image data is recorded only once, and the mode automatically enters a recording pause state.
By turning on the shutter switch 5WSH,
Image data for one frame is loaded into a memory, and this image data is recorded one or more times. To record the same image data any number of times until a recording pause state or stop state is reached.

In auto mode, the shutter is automatically turned on and
Image data for one frame is taken into memory and this image data is recorded. When recording is completed, the shutter is automatically turned on again, one frame worth of image data is captured into the memory, and this image data is recorded. This is repeated until the recording pause state or stop state is reached.

Next, details of the recording operation will be explained using the flowchart of FIG. 6.

When the recording switch 5WRE is turned on, step 101
recording pause is automatically turned on.

At this time, the changeover switch 56 is connected to the a side, and the A/D
The digital video signal DSν· from the converter 54 is transferred to the memory 62 . of the memory means 60 via the changeover switch 56 .
64 as a write signal. Also at this time,
The changeover switch 102 is connected to hI[lJ, and the A/D
The digital video signal DSv from the converter 54 is supplied to the D/A converter 104 via the changeover switch 102.
A monitor (not shown) connected to the video out terminal 108 displays a moving image (through image) based on the video signal Sv supplied to the video in terminal 50.

Next, in step 102, it is determined whether the mode is one-shot mode.

When the mode selection switch SWMO is connected to the S side and the mode is one-shot mode, it is determined in step 103 whether the shutter switch 5WSH is on. Although not mentioned above, it is assumed that the shutter switch 5WSH automatically returns to OFF.

In step 103, when the shutter switch 5WS) is on, in step 104, video data DSv for one frame is written to the memory 62, 64 with a length of 4 fsc.

Next, in step 105, video data DSv for one frame is repeatedly read out from the memory 62 with a clock of 4 fSC. At this time, the selector switch 102 is switched from the ha side to the a side, so the video data DSv for one frame read from the memory 62 is transferred to the D/A converter 104 via the selector switch 66 and ]02. A still image is displayed on the monitor supplied and connected to terminal 10.

Next, in step 106, it is determined whether the pause switch swPA is off. When it is not off, the process returns to step 103; when it is off, the process returns to step 10.
At step 7, video data DSv for one frame is read out from the memory 64 with a clock of 2 fs, and this is mixed with the digital audio signal DSa' as described above after the changeover switch is turned 6 days, and recorded as DAT. Ru.

Next, in step 108, it is determined whether recording is complete. When the recording of one frame worth of video data DSV is completed, the recording pause is automatically turned on in step 109.

Then, in step 110, the changeover switch 102
A moving image (through image) based on the video signal Sv supplied to the video in terminal 50 is displayed on the monitor connected to the video out terminal 108, and the process returns to step 103.

Also, in step 103, the shutter switch 5WSH
When is off, it is determined in step 111 whether or not a through image is being displayed on the monitor. If a still image is displayed instead of a through image, step 105
Proceed to. When the through image is being displayed, it is determined in step 112 whether the pause switch 5WPA is off.

If it is not off, the process returns to step 103. When it is off, in step 113, a still image is displayed on the monitor in the same manner as in step 105, and the process proceeds to step 107.

Furthermore, if it is determined in step 102 that the mode is not one-shot mode, it is determined in step 115 whether manual mode is selected.

When the mode selection switch SWMO is connected to the n1 position and the mode is manual mode, it is determined in step 116 whether the shutter switch 5WSH is on. When the shutter switch 5WSH is on,
In step 117, the memories 62 and 64 of the memory means 60 are
One frame worth of video data DSv is written to.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. And step】1
At step 9, it is determined whether the pause switch 5WPA is off. If it is not off, the process returns to step 116.

When it is off, the video data DSv for one frame is read out from the memory 64 in the same manner as in step 107, mixed with the digital audio signal DSa', and recorded as DAT.

Next, in step 121, it is determined whether recording is complete. When recording is completed, it is determined in step 122 whether the pause switch 5WPA is on. If it is not on, the process returns to step 11B. When it is on, in step 123, a through image is displayed on the monitor in the same manner as in step 110, and in step 11
Return to 6.

If the shutter switch 5w5u is not on in step 116, it is determined in step 124 whether or not a through image is being displayed on the monitor.

If a still image is being displayed instead of a through image, the process advances to step 11. When the through image is being displayed, it is determined in step 125 whether the pause switch 5WPA is off. If it is not off, the process returns to step 116. When it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

Further, if it is determined in step 115 that the mode is not one-shot mode, it is determined in step 128 whether or not the mode is auto mode.

When the mode selection switch SWMO is connected to the a side and the mode is auto mode, it is determined in step 129 whether the pause switch 5WPA is off. When the controller 100 is off, the step 130
After the internal shutter is turned on, step 13
1, video data DSν for one frame is written into the memories 62 and 64 of the memory means 60.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. And step 13
3, in the same way as step 107, 1 is read from the memory 64.
Video data DSV for one frame is read out, mixed with digital audio signal DSa', and recorded as DAT.

Next, in step 134, it is determined whether recording is complete. When the recording is completed, the process returns to step 129.

If it is determined in step 128 that the mode is not automatic, the process returns to step 102.

Note that when the recording switch 5WRE is turned on and the stop switch 5WST is turned on in any mote, the recording switch 5WRE is turned on and the stop switch 5WST is turned on by interrupt processing.

At this time, the changeover switch 102 is connected to BS, and a through image is displayed on the monitor.

By the way, during playback, the memory 62.6 of the memory means 60
It takes about 5 seconds to write one frame's worth of video data DSν into the memory.

Therefore, video data DSv and audio data DSa' are recorded on the tape using DAT as shown in FIG. 7A.
If the video data DSv for one frame is written in the memory 62, 64, this one frame worth of video data DSv is repeatedly read out, and the monitor ζ still image is recorded. If you want to display
The relationship between the reproduced audio and the reproduced image is as shown in FIG. In other words, the image will be displayed approximately 5 seconds after the audio is output, and the reproduction timing of the audio and the image will be significantly different.

In order to improve such timing deviation, memory 6
2. When the writing of video data DSv for one field is completed in 2.64, until the video data DSv for another field is written, the first written l It is conceivable to repeatedly read video data DSv for a field and display a still image based on a field signal on a monitor. Although not mentioned above, in the signal processing device shown in FIG. 1 as well, a still image based on a field signal is displayed at the start of playback.

When video data DSv and audio data DSa' are recorded in association with each other as shown in FIG. 7A, the relationship between reproduced audio and reproduced image becomes as shown in FIG. 7C.

In other words, the image is displayed approximately 2.5 seconds after the audio is output, and there is still a lag in the playback timing between the audio and the image.

Therefore, in this example, as shown in FIG. 8A, for one frame of video data DSv, the corresponding audio data DSa' is recorded from the time when one field is recorded. Ru. In other words, the controller 100 outputs a synchronization signal as shown in FIG. Signal S aL,
The supply timing of S aR is controlled.

Note that depending on the timing of the synchronization signal, the light emitting element,
For example, the user may be informed of the timing of voice input by lighting an LED.

In this example, the recording timings of the video data DSV and the audio data DSa' are shifted by about one field period, so the relationship between the reproduced image and the reproduced audio becomes as shown in FIG. The playback timing of the audio and audio will now match.

By the way, in the DAT, the program number for search is recorded in the subcode area of the track format (shown in FIG. 9).

The scanning locus of the head during the search (FF search, REW search) spans several tracks, as shown by solid line arrows in FIGS. 10A and 10B. Therefore, for example, during a 200x search, the probability that the head will pass through the subcode area is 9.
This is only three times per second (recording time of the same program number on the current DAT).

Taking into consideration that the sub-code can be read without error using a 200x search, it is difficult to shorten the recording time of 9 seconds.

On the other hand, as mentioned above, one frame's worth of video data DS
v is recorded in DAT in about 5 seconds. Therefore, if a program number is assigned corresponding to approximately 5 seconds in which video data DSv for each frame is recorded, 200
Double search becomes impossible.

Furthermore, if a program number is assigned every 5 seconds, a 2-hour DAT tape will require 1400 or more program numbers.

Therefore, a program number is assigned corresponding to about 5 seconds in which video data DSv for each frame is recorded, and in addition to the areas of program numbers 1 to 3,
A four-digit program number is assigned using half of the index number area (see the pack format in Figure 11).

When a 4-digit program number is added every approximately 5 seconds, the upper 3 digits of the 4-digit program number remain the same for approximately 50 seconds. D.A.
The search in T is performed using this fact.

FIG. 12 shows the configuration of the parts involved in the DAT search.

In the figure, a reproduced signal from the head is supplied to a sub-coat processing circuit 201, and this sub-coat processing circuit 201
The program number data DPR from is supplied to the CPU 202.

Further, 204 is a capstan motor, and a frequency signal SFG from a frequency generator FG attached to this motor 204 is supplied to a capstan control circuit 203. The control circuit 203 controls the rotational speed and direction of the motor 204. The operation of the control circuit 203 is based on the program number data DPR.
202.

When searching for a certain 4-digit program number,
Utilizing the fact that the upper three digits of the four-digit program number remain the same for about 50 seconds, the upper three digits are searched by a 200x search. In other words, the sub coat processing circuit 201
If the upper three digits of the program number indicated by the data DPR supplied to the CPU 202 match the target value,
A 200x search is performed.

Next, when the top three digits match the target value, the CPU2
The control circuit 203 is controlled by 02, and a 16 times search is performed. That is, the 16x search is performed until all digits of the program number indicated by the data DPR match the target value.

Fig. 13 shows the operation when searching for program number 1254, in which a 200x search (high speed search) searches for parts 1250 to 1259, and then a 16x search (low speed search) searches for 1254. part is searched.

Note that the 200x and 16x searches are just examples, and the speed is not limited to these as long as the speed is such that the upper three digits and all digits of the program number can be read, respectively.

By the way, it is difficult to use the signal processing device shown in FIG. When performing digital dihing using A'r, the digital video signal DSν of the lower 8 bits should be recorded as is, and the digital audio signal DSa' of the upper 8 bits should be replaced with other content before recording. is possible.

FIG. 14 shows a configuration for digital dihing using two DATs.

In the figure, 301 is the DAT on the master side;
02 is a DAT on the slave side. The digital signal DSm (shown in FIG. 16A, see the second diagram) output from the DAT 301 is transferred to the D
The signal is supplied to the AT 302 as a recording signal, and is also supplied to the DAT 302 as a recording signal via the b side of the changeover switch 303 and the dubbing device 304.

In addition, the pit clock BC output from DAT301
K (shown in FIG. 16C) and a clock LRCK (shown in FIG.
4.

Further, left and right channel audio signals S aL and S sR are supplied to the dubbing device 304 .

151st! 1 is a diagram showing a specific configuration of the dubbing device 304.

In the same figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is the al! of the changeover switch 341. is supplied to the fixed terminal of l.

Clock BCK and LRCK from DAT 301 are supplied to timing generation circuit 343.

Further, the left and right channel audio signals SaL and SaR are supplied to a signal processing circuit 342. This signal processing circuit 3
42 is supplied with the clock LRCK, and is also supplied with a clock of frequency fs from the timing generation circuit 343.

This signal processing circuit 342 is the amplifier 9L in FIG.
, 9R to compression circuit 14, and outputs an 8-bit compressed digital audio signal DSa' (shown in Fig. 16 and Fig. 2B!). This digital audio signal DSa' is transferred to the selector switch 34.
1 bm fixed terminal.

Furthermore, the timing generation circuit 343 uses a clock BCK.
, LRCK, the digital signal DSm has a low level "60'" corresponding to the video signal DSv, and a high level "1" corresponding to the audio signal DSa, and the state changes every 8 bit clocks. A clock WCK (shown in FIG. 16) is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to the a side when the clock WCK is at a low level "0", and is connected to the bs side when the -blade height level is "1".

As a result, the changeover switch 341 outputs the digital signal DSs (shown in FIG.
becomes the output signal.

] Returning to Figure 4, when dubbing, the selector switch 303
When connecting the DAT 301 to the a side, the digital signal DSm output from the DAT 301 is directly supplied to the DAT 302 and recorded.

Furthermore, when the selector switch 303 is connected to the b side during dubbing, the digital signal DSs output from the dubbing device 304 is supplied to the DAT 302 and recorded. In other words, audio dubbing processing is performed.

In the above-mentioned embodiment, the audio signal DSa' is arranged in the upper 8 bits and the video signal DSv is arranged in the lower 8 bits for the total number of bits of 16 for recording and reproduction, but the number of bits and the arrangement position are different. Of course, it is not limited to this.

Further, in the above-described embodiments, the audio signal is compressed and recorded, but the present invention can be similarly applied to audio signals that are recorded without being compressed.

Further, in the above embodiments, the recording medium is a magnetic tape, but it may also be a magnetic disk or one that can be recorded and reproduced optically.

[Effects of the Invention] As described above, according to the present invention, a digital audio signal can be replaced with a secondary digital audio signal during dubbing, and audio dubbing processing can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal processing device, FIG. 2 is a diagram showing an example of the format of a digital signal, FIG. 3 is a diagram showing the structure of recording data, and FIG. 4 is an explanatory diagram of sync bit shift processing. Fig. 5 is an explanatory diagram of the most significant bit inversion, Fig. 6 is a flowchart showing the recording operation, Figs. 7 and 8 are explanatory diagrams of the reproduction timing of images and audio, and Figs. 9 to 13.
The figure is a diagram for explaining the search, and FIGS. 14 to 16 are diagrams for explaining the audio dubbing. 14... Compression circuit 20... Mixing means 36... Separation means 38... Expansion circuit 62,64... Memory means 80... Identification code generator 94... Identification coat detector 201.・・Subcode processing circuit 202・IφCPU 203・・Capstan control circuit 204・Capstan motor 301.302 Command・War DAT 304・・・・Track formant of dubbing equipment DAT Figure 9 Sir Chigin's Quantitative Figure 10 No Heart Nkufu 7-Ma Soto Figure 11 DAT Noriichi I¥ITru fP Minute Figure 12

Claims (1)

[Claims] (1) The N+M bits are reproduced from a recording medium on which an N+M bits digital signal is recorded by combining an N bits (N is an integer) digital audio signal and an M bits (M is an integer) digital video signal. In a dubbing device for recording a digital signal on another recording medium, the N-bit digital audio signal constituting the N+M-bit digital signal reproduced from the first recording medium is combined with another N-bit digital audio signal. A dubbing device characterized by comprising a means for exchanging.