JPH0447874A - Still picture recorder - Google Patents

Abstract

PURPOSE:To automatically obtain the monitor state by providing a switch circuit to the recorder, which selects a picture data from a memory for the output purpose at the time of recording and selects an input video signal for the output purpose in the pause or stop mode. CONSTITUTION:A still picture use video signal Sv fed to a terminal 50 is given to an amplifier 52 and an A/D converter 54, which uses a sampling clock of 4fsc (fsc is 3.5MHz). An output signal DSv is fed to a memory means 60 via a changeover switch 56. Wrote and read of memories 62, 64 are implemented by a controller 100. With a switch SWPL turned on, the reproduction mode is selected, the video signal DSv is read repetitively and a still picture is displayed on a monitor. A switch SWRE closed, the recording mode is selected. At the recording, a switch SWMO selects the one-shot, the manual and the automatic mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention provides a method of
Image data for a screen is captured into a memory, and this image data is sequentially read out from the memory and transferred to a still image recording device for recording.

[Prior art] The current digital audio tape recorder (hereinafter referred to as "D")
(referred to as "AT") is designed to record and reproduce only audio signals.

However, since it would be very convenient to record and play back not only audio signals but also other signals, such as video signals for still images, the applicant first synthesized digital audio signals and digital video signals. , proposed simultaneous recording and playback.

[Problems to be Solved by the Invention] Regarding digital video signals, for example, when the shutter is turned on, one screen worth of image data is taken into the memory from the input video signal. Then, this image data is sequentially read out from the memory, combined with a digital audio signal, and recorded.

In this case, during recording, it is desirable to be able to monitor the image based on the image data that is captured into the memory and recorded, in order to know what kind of image data will be recorded. In selecting images to record, it is desirable to be able to monitor images from the input video signal.

Therefore, the present invention provides a still image recording device that can automatically obtain the above-mentioned monitor state.

[Means for Solving the Problems] The present invention provides a method for solving the problems when the shutter is turned on by
In a still image recording device that captures image data for a screen into a memory, and sequentially reads and records this image data from the memory, when recording after the shutter is turned on, the image data read from the memory is selected and output, and the recording pause state is reached. Alternatively, in a stopped state, a switch circuit is provided to select and output an input video signal.

[Function] In the above configuration, by connecting a monitor to the output side of the switch circuit, it is possible to monitor the image based on the image data read from the memory during recording after the shutter is turned on, and to monitor the input video signal in the recording pause state or stop state. images can be monitored.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

In this example, the analog audio signal is 1 sample 1
0-bit digital audio signal DSa [A9 to A
O] (shown in FIG. 2A), and further converted into a one-sample 8-bit digital audio signal DSa' [A
? '~AO'] (shown in FIG. 1B).

Further, the analog video signal is converted into a digital audio signal DSv [V7 to VO] of 8 bits per sample (as shown in C in the same figure).

The second diagram shows the format of the digital signal DS recorded and reproduced in this example.

Among the 16-bit data D15 to DO, the upper 8 bits contain a digital audio signal DSa' [A? '〜A
O'] is arranged, and a digital video signal DSv[V7 to VO] is arranged in the lower 8 bits.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, is recorded on a magnetic tape, and is reproduced from the magnetic tape.

As will be described later, in the DAT, both the left (L) channel and right (R) channel digital audio signals DSa sampled at the clock fs are sequentially recorded. Therefore, each sample data of the digital video signal DSv is mixed with the digital audio signal DSa and recorded in synchronization with the clock 2fs.

48kHz as audio sampling clock fs
Using , the video sampling clock is set to 4 f
sc (NTSC method, fsc is 3.58MH
z), the video sampling clock 4 f
There is a frequency difference of about 149 times between sc and the clock 2fs described above. That is, 1/4
Each sample data of the digital video signal DSv sampled at a period of fsc is 1/2fs (1/2fs).
The data are sequentially recorded at a period of about 149 times 4fsc).

Therefore, since one frame period is 1/30 second, 1 frame period is 1/30 second, so 1
It will take approximately 4.96 seconds to record a frame (odd and even fields) of video signal. Moreover, as will be described later, since an identification code ID is added to the video signal, one frame of the video signal is finally recorded for approximately 5 seconds.

FIG. 3 is a diagram showing the data structure. In other words, immediately before the video signal of each of the odd (ODD) and even (EVEN) fields that make up one screen, there is a start code S/ID indicating the start of data, and a motto to distinguish between odd and even fields. Code MD-ID,
A last start code LS/ID is added to distinguish the identification code from the data. Furthermore, a stop code E-ID indicating the end of data is added immediately after the video signal of each field.

For example, the start code 5-ID is composed of 8-t data in which only the least significant bit is "1", and the stop code E-ID is composed of 8-t data in which all bits are "0".

FIG. 1 shows an example of a signal processing device for forming a digital signal DS having a format as shown in FIG. 2 and recording and reproducing it on a DAT even if the data structure is as shown in FIG.

First, a signal processing system for audio signals will be explained.

Left and right channel audio signals SaL and SaR supplied to audio in terminals 8L and 8R are amplifier 9L.
, amplified by 9R, noise reduction circuit 10L
, IOR removes noise, and low-pass filter IIL
, IIR band-limited.

Then, it is supplied to the A/D converters 12L and 12H.
Bit digital audio signals DSaL, DSaR
is converted to An audio sampling clock fs (48kHz) is supplied to the A/D converters 12L and 12R.

Digital audio signals DSaL and DSaR output from the A/D converters 12L and 12R are supplied to the L side and the R side of the changeover switch 13, respectively.

A clock LRCK with a frequency of 48 kHz and a duty of 50% is supplied to this changeover switch 13, and the frequency is 1/96.
It is alternately switched to Ll and R11 every kHz period.

The digital audio signal DSa output from the changeover switch 13 is supplied to a compression circuit 14, where it is converted from a signal of 10 bits per sample to a signal of 8 bits per sample.

The digital audio signal DSa' converted into an 8-bit signal by the compression circuit 14 is supplied to a mixing means (adder) 20 constituting the mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later.

The mixed digital signal DS (shown in the second diagram) is then supplied to the digital out processing circuit 22,
It is converted into a digital signal in a form compliant with the AT audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a pit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head (not shown) of the DAT via the digital out terminal 24 and recorded thereon.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a digital-in terminal 32, and subjected to digital-in processing. For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the next-stage separation means 36 outputs the digital audio signal DSa' (shown in FIG. 2B) and the digital The video signal DSv (shown in C of the same figure) is separated and output.

The 8-bit digital audio signal DSa' separated every 1/96 kHz by the separation means 36 is supplied to an expansion circuit 38. In this expansion circuit 38,
The digital audio signal DSa, which has been made into a 10-bit signal by the decompression circuit 38, undergoes processing opposite to that of the compression circuit 14, and the 1-sample 8-bit signal is returned to the 1-sample 10-bit signal. As soon as the clock LRCK is supplied to the movable terminal of switch 39, the clock LRCK is supplied to the changeover switch 39, and the clock LRCK is
side and R side alternately.

That is, the left and right channel digital audio DSaL and DSaR are obtained at the fixed terminals on the L side and the R side of the changeover switch 39, respectively, with a cycle of ]/48 kHz.

The digital audio DSaL and DSaR output from the changeover switch 39 are output from the D/A converter 40L140.
It is supplied to H and converted into an analog signal.

An audio sampling signal fs is supplied to the A/D converters 4OL and 4OR.

The audio signals S aL and S aR output from the D/A converters 40L and 4OR are passed through a low-pass filter 4I.
L, 41R are band limited and noise reduction circuit 4
After the noise is removed by 2L and 42R, it is further amplified by amplifiers 43L and 43R and sent to audio out terminal 4.
Output to 4L and 44H.

Next, a signal processing system for video signals will be explained.

The still image video signal Sv supplied to the video in terminal 50 is amplified by an amplifier 52 and then sent to an A/D converter 5.
4, and one sample is converted into an 8-bit digital signal. This A/D converter 54 has 4 f sc
(f sc is the subcarrier frequency, 3.58M
H2) sampling clock is used.

The digital video signal DSv output from the A/D converter 54 is supplied to a fixed terminal on the e side of a changeover switch 56 that switches between an input signal and a reproduction signal. The output signal of this changeover switch 56 is supplied to memories 62 and 64 constituting the memory means 60 as a write signal.

The memories 62 and 64 each have a storage capacity for one frame. Writing and reading of these memories 62 and 64 are controlled by supplying control signals to memory control circuits 70 and 72 from a controller 100 having a CPU.

The video signal Sv supplied to the terminal 50 is supplied to a subcarrier extraction circuit 110 via an amplifier 52, and the subcarrier fsc extracted by this extraction circuit 110 is supplied to the controller 100. Further, the digital video signal DSv output from the A/D converter 54 is supplied to a vertical synchronization separation circuit 112, and the vertical synchronization signal separated by this separation circuit 112 is supplied to the controller 100. Control signals are supplied to the memory control circuits 70 and 72 based on the subcarrier fsc, the vertical synchronization signal, and the bit clock BCK.

In this case, during recording, writing to the memory 62, 64 is performed with a clock of 4 f sc, and reading is performed with a clock of 2 f sc to one memory, and a clock of 4 f sc to the other memory.
This is done using the fsc clock. In other words, one memory functions as a time-closed axis compression means for the digital video signal DSv since it combines the digital video signal DSv with the digital audio signal DSa mentioned above.

Also, during playback, writing to the memories 62 and 64 is performed using a clock with a frequency of 2fs, and
The reading is performed with a clock of 4 fsc. In other words, the memories 62 and 64 function as time axis expansion means for the digital video signal DSv.

The signal read from the memory 62 is transferred to the selector switch 66.
．． A signal supplied to the fixed terminal on the e side of the switch 68 and read out from the memory 64 is supplied to the fixed terminal on the f side of the changeover switch 66 and 68. Switching of these changeover switches 66 and 68 is controlled by a controller 100.

The digital video signal DSv output from the changeover switch 68 is supplied to a sync bit shift encoder 76, where a sync bit shift process is performed.

Originally, a video signal is A/D converted into 8 bits, so its sync bits are digital data in which all bits are "0". However, since the identification code ID is assigned to bits that do not affect the image as described above, the encoder 76 shifts the sync bit by one bit so that the identification code ID and the sync bit can be distinguished. (See Figure 4).

The digital video signal DS'v, on which the sync bits have been shifted by the encoder 76, is supplied to an adder 78, where an identification code 1" ID is added (see FIG. 3). , identification code F' I
This is the generator of D.

The digital video signal DSv to which the identification code F'ID is added by the adder 78 is subjected to parallel/serial conversion processing in the signal processing circuit 82, and is converted into a digital video signal D.
Bit inversion processing is performed on the MSB (most significant bit of Sv). This process will be described later.

The digital video signal DSv, which has undergone predetermined signal processing in the signal processing circuit 82, is mixed with the digital audio signal DSa' by the mixing means 20, as shown in the second figure, and sent to the DAT side.

Furthermore, when reproducing the digital signal DS, the separating means 36
The digital video signal DSv separated by is subjected to serial/parallel conversion processing in the signal processing circuit 90, and also inversion processing of the most significant bit (MSB) of the digital video signal DSv is performed.

Then, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite manner to the recording process, and after returning to the original sync bits (see FIG. 4), the changeover switch 56
is supplied to the fixed terminal of bIl.

Switching of the changeover switch 56 is controlled by the controller 100, and it is connected to all during recording and to the b side during playback.

Further, the digital video signal DSv output from the changeover switch 66 is supplied to the fixed terminal on the g side of the changeover switch 102, and the output signal of the A/D converter 54 is supplied to the fixed terminal on the h side. This switching of the changeover switch 102 is controlled by the controller 100. In other words, when displaying a moving image (through image) during recording, ha
When displaying a still image to be recorded, it is connected to the g side. During playback, it remains connected to gll.

The digital video signal DSv output from the changeover switch 102 is converted into an analog signal by the D/A converter 104, and then sent to the video out terminal 1 via the amplifier 106.
It is output on 08. On this terminal 10th, monitor means (
0) (not shown) is connected.

Further, the output signal of the signal processing circuit 90 is supplied to an identification code detector 94. The identification code ID detected by the detector 94 is supplied to the controller IGO. Based on this identification code ID, the memory control circuit 70.72
is controlled.

During playback, when the digital video signal DSv to which the identification code ID is added is played back and stored in the memory means 60, only image data is stored. At that time, in both odd and even fields, the final data is when a predetermined period of time has elapsed from the first data of the image data.
In order to detect this final data more accurately, in addition to management based on time, a stop code E-ID is detected, and when the two match, it is determined as final image data.

Then, when the writing of the final image data of the even field is completed, the writing and reading modes of the memory 62, 64 are reversed, and the changeover switch 66, 68 is reversed.
can also be switched to the opposite side.

By the way, during the reproduction of the digital video signal DSv, the DA
When the reproduction of T is stopped, all bits of the reproduced output data supplied to the terminal 32 become "0" as shown in FIG.

Since time management (count-up processing) for image data is performed on the signal processing device side shown in Fig. 1, the DA
Even if the reproduction of T is stopped, the count-up process does not stop in conjunction with this.

Therefore, for example, the memory 64 is kept in the write state as usual, and data of all bits "0" is written to one memory l of the memory means 60 as original image data. When a predetermined time elapses from the stop mode of the DAT, the playback time for the final image data of the even field arrives, and all bits of the playback data at that time are always "o", so this is set as the stop code E. - Misjudged as ID. As a result, the signal processing device considers that the final image data has arrived, and selects the changeover switch 66.
68 is switched, and the memory 64 is controlled to read mode.

Then, while the DAT is in stop mode, all the bits "o" data written in the memory 64 are read out and displayed as a black image, resulting in a very unsightly image being monitored. Become.

In order to avoid this, if the most significant hit of the image data is inverted and recorded as described above and then inverted again during playback, as shown in Figure 5, all bits of the playback output data when stopped midway will be
Even if it is "0", the most significant bit MSB becomes "1" when re-inversion processing is performed.

As a result, the signal processing device side does not judge that the final screen data has arrived, and the memory means 60 does not perform switching control, so the previous screen is always monitored, and the above-mentioned drawbacks are avoided. removed.

The controller 100 also includes a shutter switch 5.
WSH1 Record switch 5WRE, Playback switch SW
PL, pause switch SW PA, stop switch 5WST, and recording mode selection switch SWM
O is connected.

When the playback switch 5WPL is turned on, it is the time of playback. As a result, the DAT is placed in a playback state, and
The changeover switch 56 is connected to the b side.

The reproduced digital video signal DSv is written into one of the memories 62 and 64 via the changeover switch 56 with a clock of 2 fs. While being written into one of the memories 62 and 64, the digital video signal DSv for one frame is repeatedly read out from the other memory with a clock of 4 fsc, and the changeover switches 66 and 10
After the signal is supplied to the D/A converter 104 through 2 and converted into an analog signal, it is supplied to a monitor to display a still image.

When one field's worth of final image data is written into one memory, the write/read modes of the memories 62 and 64 are reversed, and the selector switch 66 is also switched.

As a result, the reproduced digital video signal DSv is now written to the other memory with a clock of 2fs, and the digital video signal DSv for one frame is repeatedly written from one memory with a clock of 4fsc. The still image is read out and displayed on the monitor.

Thereafter, reading and writing to and from the memories 62 and 64 are repeated as described above.

Next, when the recording switch 5WRE is turned on, it is time for recording. As a result, the DAT is placed in a recording state, and the changeover switch 56 is connected to the a side.

During this recording, the mode selection switch SWMO is
When connected to the sll, mll, and a sides, respectively, the modes are one-shot mode, manual mode, and auto mode.

In one shot mode, shutter switch 5WSH
By turning on, the image data for one frame is loaded into the memory, and this image data is recorded only once.
Automatically enters recording pause state.

In the manual mode, by turning on the shutter switch 5WSH, image data for one frame is captured into the memory, and this image data is recorded one or more times.

To record the same image data any number of times until a recording pause state or stop state is reached.

Automote automatically turns on the shutter and
Image data for one frame is taken into memory and this image data is recorded. When the recording is completed, the shutter is automatically turned on again, one frame of image data is taken into the memory, and the second image data is recorded. This is repeated until the recording pause state or stop state is reached.

Next, details of the recording operation will be explained using the flowchart of FIG. 6.

When the recording switch 5WRE is turned on, step 101
The recording pause is automatically turned on.

At this time, the changeover switch 56 is connected to the a side, and the A/D
The digital video signal DSv from the converter 54 is transferred to the memory 62.6 of the memory means 60 via the changeover switch 56.
4 as a write signal. Also, at this time, the changeover switch 102 is connected to the a side, and the A/D converter 54
The digital video signal DSv from the selector switch 10
A monitor (not shown) connected to the video out terminal 108 is supplied to the D/A converter 104 through the valve 2.
A moving image (through image) based on the video signal Sν supplied to the video-in terminal 50 is displayed.

Next, in step 102, it is determined whether the mode is one-shot mode.

When the mote selection switch SWMO is connected to the S side and the mode is one-shot mode, it is determined in step 103 whether the shutter switch 5WSH is on. Although not mentioned above, it is assumed that the shutter switch 5WSH automatically returns to OFF.

When the shutter switch 5WSH is on in step 103, the video data DSv for one frame is written in the memory 62, 64 with a clock of 4 f sc in step 104.

Next, in step 105, video data DSv for one frame is repeatedly read out from the memory 62 with a clock of 4 fSC. At this time, the changeover switch 102 is switched from the h side to gll, so the video data DSv for one frame read from the memory 62 is supplied to the D/A converter 104 via the changeover switch 66.102. A still image is displayed on the monitor connected to the terminal 108.

Next, in step 106, it is determined whether the pause switch 5WPA is off. When it is not off, the process returns to step 103; when it is off, the process returns to step 10.
At step 7, one frame worth of video data DSv is read out from the memory 64 with a clock of 2 fs, and this is mixed with the digital audio signal DSa' as described above through the changeover switch 68 and recorded as DAT. .

Next, in step 108, it is determined whether recording is complete. When recording of video data DSV for one frame is completed, the recording pause is automatically turned on in step 109.

Then, in step 110, the changeover switch 102
A moving image (through image) based on the video signal Sv supplied to the video in terminal 50 is displayed on the monitor connected to the video out terminal 108, and the process returns to step 103.

Also, in step 103, the shutter switch 5WSH
When is off, it is determined in step 111 whether or not a through image is being displayed on the monitor. If a still image is displayed instead of a through image, step 105
Proceed to. When the through image is being displayed, it is determined in step 112 whether the pause switch 5WPA is off.

If it is not off, the process returns to step 103. When it is off, in step 113, a still image is displayed on the monitor in the same manner as in step 105, and in step 10? Proceed to.

Further, if it is determined in step 102 that the mode is not one-shot mode, it is determined in step 115 whether or not the mode is manual mode.

When the mode selection switch SWMO is connected to mll and the mode is manual mode, it is determined in step 116 whether the shutter switch 5WSH is on. When the shutter switch 5WSH is on,
In step 117, the memory 62, 64 of the memory means 60
One frame worth of video data DSv is written to.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. And step 11
At step 9, it is determined whether the pause switch 5WPA is off. If it is not off, the process returns to step 116.

When it is off, the video data DSv for one frame is read out from the memory 64 in the same manner as in step 107, mixed with the digital audio signal DSa', and recorded on the DAT.

Next, in step 121, it is determined whether recording is complete. When recording is completed, it is determined in step 122 whether the pause switch 5WPA is on. If it is not on, the process returns to step 118. When it is on, a through image is displayed on the monitor in step 123 in the same manner as in step 110, and in step 116
Return to

If the shutter switch 5WSH is not on in step 116, it is determined in step 124 whether or not a through image is being displayed on the monitor.

When a still image is displayed instead of a through image, the process advances to step 11B. When the through image is being displayed, it is determined in step 125 whether the pause switch 5WPA is off. If it is not off, the process returns to step 116. When it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

Further, if it is determined in step 115 that the mode is not one-shot mode, it is determined in step 128 whether or not the mode is auto mode.

When the mode selection switch SWMO is connected to all and the mode is auto mode, it is determined in step 129 whether the pause switch 5WPA is off. When it is off, in step 130 the controller 10
After the internal shutter of 0 is turned on, step 1
At step 31, video data DSv for one frame is written into the memories 62 and 64 of the memory means 60.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. And step 13
3, in the same way as step 107, 1 is read from the memory 64.
Video data DSV for one frame is read out, mixed with digital audio signal DSa', and recorded as DAT.

Next, in step 134, it is determined whether recording is complete. When the recording is completed, the process returns to step 129.

If it is determined in step 128 that the mode is not automatic, the process returns to step 102.

Note that when the recording switch 5WRE is turned on and the stop switch 5WST is turned on while the recording switch 5WRE is in any mode, the recording switch 5WRE is turned on and the stop switch 5WST is turned on by interrupt processing.

At this time, the changeover switch 102 is connected to the h side, and a through image is displayed on the monitor.

By the way, during playback, the memory 62.6 of the memory means 60
It takes about 5 seconds to write one frame worth of video data DSv to the memory card 4.

Therefore, video data DSv and audio data DSa' are recorded on the tape using DAT as shown in FIG. 7A.
If the video data DSv for one frame is written in the memory 62, 64, this video data DSv for one frame is repeatedly read out and a still image is displayed on the monitor. If they are to be displayed, the relationship between the reproduced audio and the reproduced image will be as shown in Figure B.

In other words, the image will be displayed approximately 5 seconds after the audio is output, and the reproduction timing of the audio and the image will be significantly different.

In order to improve such timing deviation, memory 6
2. When the writing of video data DSv for one field is completed in 64, until the video data DSv for another field is written, the first written field is It is conceivable to repeatedly read out the video data DSv for 30 minutes and display a still image based on a field signal on a monitor. Although not mentioned above, in the signal processing device shown in FIG. 1 as well, a still image based on a field signal is displayed at the start of playback.

When the audio data DSv and the audio data DSa' are recorded in association with each other as shown in FIG. 7A, the relationship between the reproduced audio and the reproduced image becomes as shown in FIG. 7C.

In other words, the image is displayed approximately 2.5 seconds after the audio is output, and there is still a lag in the playback timing between the audio and the image.

Therefore, in this example, as shown in FIG. 8A, for one frame of video data DSv, the corresponding audio data DSa' is recorded from the time when one field is recorded. Ru. In other words, when the recording of the image data DSv of the odd field is completed, the controller 100 outputs a synchronization signal as shown in FIG. audio signals SaL, SaR
supply timing is controlled.

Note that depending on the timing of the synchronization signal, the light emitting element,
For example, the user may be informed of the timing of voice input by lighting an LED.

In this example, the recording timings of the video data DSV and the audio data DSa' are shifted by approximately 1 field F' 131, so the relationship between the reproduced image and the reproduced audio is as shown in FIG. This means that the playback timings of the image and audio will match.

By the way, in the DAT, the search program number is recorded in the subcode area of the track format (shown in FIG. 9).

The scanning locus of the head during search (FF search, REW search) spans several tracks, as shown by solid line arrows in FIGS. 10A and 10B. Therefore, for example, during a 200x search, the probability that the head will pass through the subcode area is 9.
This is only three times per second (the recording time of the same program number on the current DAT).

Taking into account that the sub-code can be read without error using a 200x search, it is difficult to shorten the recording time of 9 seconds.

On the other hand, as mentioned above, the video data DS for one frame
v is recorded in DAT in about 5 seconds. Therefore, if a program number is assigned corresponding to approximately 5 seconds in which video data DSv for each frame is recorded, 200
Double search becomes impossible.

Furthermore, if a program number is assigned every approximately 5 seconds, a 2-hour DAT tape will require 1400 or more program numbers.

Therefore, a program number is assigned corresponding to about 5 seconds in which video data DSv for each frame is recorded, and in addition to the areas of program numbers 1 to 3,
A four-digit program number is attached using half of the index number area (see back format in FIG. 11).

When a 4-digit program number is added every approximately 5 seconds, the upper 3 digits of the 4-digit program number remain the same for approximately 50 seconds. D.A.
The search in T is performed using this fact.

FIG. 12 shows the configuration of the parts involved in the DAT search.

In the figure, a reproduced signal from the head is supplied to a subcode processing circuit 201, and this subcode processing circuit 201
Program number data from DPR1, tCPU20
2.

Further, 204 is a capstan motor, and a frequency signal SFG from a frequency generator FG attached to this motor 204 is supplied to a capstan control circuit 203. This control circuit 203 controls the rotation speed and rotation direction of the motor 204. The operation of the control circuit 203 is based on the program number data DPR.
202.

When searching for a certain 4-digit program number,
Utilizing the fact that the upper three digits of the four-digit program number remain the same for about 50 seconds, the upper three digits are searched by a 200x search. In other words, the subcode processing circuit 201
Until the upper three digits of the program number indicated by the data DPR supplied to the CPU 202 match the target value,
A 200x search is performed.

Next, when the top three digits match the target value, the CPU2
The control circuit 203 is controlled by 02, and a 16 times search is performed. That is, the 16x search is performed until all digits of the program number indicated by the data DPR match the target value.

Figure 13 shows the operation when searching for program number 1254, in which the 1250 to 12590 portion is searched with a 200x search (high speed search), and then the 1254 portion is searched with a 16x search (low speed search). is searched.

Note that the 200x and 16x searches are just examples, and the speed is not limited to these as long as the speed is such that the upper three digits and all digits of the program number can be read, respectively.

By the way, by using the signal processing device shown in the example in FIG. 1, a tape in which a digital audio signal DSa and a digital video signal DSv are mixed and recorded on a DAT can be digitally dubbed using two DATs. , the lower 8 bits of the digital video signal D
It is conceivable that Sv is recorded as is, and the upper 8 bits of the digital audio signal DSa' are replaced with other contents.

FIG. 14 shows a configuration for digital dubbing using two DATs.

In the figure, 301 is the DAT on the master side;
02 is a DAT on the slave side. The digital signal DSm (shown in FIG. 16A, see D11 in FIG. 2) output from the DATaO2 is supplied as a recording signal to the DAT 302 via the a side of the selector switch 303, and is also supplied to the DAT 302 as a recording signal via the a side of the selector switch 303. The signal is then supplied to the DAT 302 as a recording signal via the post-recording device 304.

In addition, the pit clock BC output from DAT301
K (shown in FIG. 16C) and a clock LRCK (shown in FIG.
4.

Further, left and right channel audio signals S aL and S sR are supplied to the dubbing device 304 .

FIG. 15 is a diagram showing a specific configuration of the post-recording device 304.

In the figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is supplied to the fixed terminal on the a side of the changeover switch 341.

Clock BCK and LRCK from DAT 301 are supplied to timing generation circuit 343.

Further, the left and right channel audio signals SaL and SaR are supplied to a signal processing circuit 342. This signal processing circuit 3
42 is supplied with the clock LRCK, and is also supplied with a clock of frequency fs from the timing generation circuit 343.

This signal processing circuit 342 is the amplifier 9L in FIG.
, 9R to compression circuit 14, and outputs an 8-bit compressed digital audio signal DSa' (shown in FIG. 16, see FIG. 2B). This digital audio signal DSa' is transferred to the selector switch 34.
1 bll's fixed terminal.

Further, in the timing generation circuit 343, the clock BCK
, LRCK, the digital signal DSm becomes a low level "0" corresponding to the video signal DSv, and becomes a high level "1" corresponding to the audio signal DSa,
Word clock W whose state changes every 8 bit clocks
CK (shown in Figure 16E) is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to aIII when the clock WCK is at a low level "OII", and is connected to bgg when it is at a high level "1".

As a result, the changeover switch 341 outputs a digital signal DSs (shown in FIG.
becomes the output signal.

Returning to FIG. 14, when dubbing, the selector switch 303
When connected to all, the digital signal DSm output from the DAT 301 is supplied as is to the DAT 302 and recorded.

Furthermore, when the selector switch 303 is connected to the b side during dubbing, the digital signal DSs output from the dubbing device 304 is supplied to the DAT 302 and recorded. In other words, audio dubbing processing is performed.

In the above-mentioned embodiment, the audio signal DSa' is arranged in the upper 8 bits and the video signal DSv is arranged in the lower 8 bits for the total number of bits of 16 for recording and reproduction, but the number of bits and the arrangement position are different. Of course, it is not limited to this.

Further, in the above-described embodiments, the audio signal is compressed and recorded, but the present invention can be similarly applied to audio signals that are recorded without being compressed.

Further, in the above-described embodiments, a magnetic tape is used for recording and reproducing, but a magnetic disk or an optical recording and reproducing device may be used.

[Effects of the Invention] As described above, according to the present invention, during recording after the shutter is turned on, it is possible to monitor the image based on the image data read out from the memory, and in the recording pause state and stop state, it is possible to monitor the image based on the input video signal. Can be monitored.

In other words, it is possible to obtain a still image recording device that allows the user to monitor the image desired by the user and is extremely user-friendly.

4.TI! Brief explanation of i-side Figure 1 is a diagram showing the configuration of the signal processing device, Figure 2 is a diagram showing an example of the format of a digital signal, Figure 3 is a diagram showing the configuration of recorded data, and Figure 4 is a diagram showing the configuration of the sync bit. An explanatory diagram of shift processing, FIG. 5 is an explanatory diagram of most significant bit inversion, FIG. 6 is a flowchart showing recording operation, FIGS. 7 and 8 are explanatory diagrams of image and audio playback timing, and FIGS. 13th
The figure is a diagram for explaining the search, and FIGS. 14 to 16 are diagrams for explaining the audio dubbing.

62.64 ・Compression circuit ・Mixing means ・Separation means ・Extension circuit ・Memory means ・Identification code generator ・Identification code detector ・Subcode processing circuit ・CPU 203...Capstan control circuit 204...Capstan motor 301.302 ・--DAT 304・War・Dub recording equipment DAT track fee mat Figure 9 Wa Sengin no he/n ← scan Figure 10 Nozutsukufu T-Ma Soto Figure 11 7-1000 part of DAT Figure 12

Claims (1)

[Claims] (1) In a still image recording device that captures one screen worth of image data from an input video signal into a memory when the shutter is turned on, and sequentially reads and records this image data from the memory, when recording after the shutter is turned on, the image data is read from the memory. What is claimed is: 1. A still image recording apparatus comprising a switch circuit for selecting and outputting image data to be inputted, and for selecting and outputting the input video signal in a recording pause state or stop state.