JPH0447596A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the danger of over deletion by applying high pressure applied from the outside at the time of data deletion to the source of a memory transistor and also applying the same degree of high pressure to a drain. CONSTITUTION:A bit line high pressure switch 400 is provided between a memory array 1 and a source line switch 150, and a boosting circuit 500 is provided between the bit line high pressure switch 400 and a switch circuit 600. High pressure Vpp outputted from the switch circuit 600 at the time of data deletion is applied not only to the source line switch 150 but also to the boosting circuit 500. Therefore, since the high pressure is applied not only to a source 230 but also to a drain 220 at the time of data deletion, the electric potential of a floating gate 210 becomes higher than the conventional one. Thus, the strength of an electric field over between the floating gate and the secure 230 is alleviated so that the energy consumption at the time of data deletion can be reduced and the danger of over deletion can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device that can be electrically written and erased.

[Prior Art] Semiconductor storage devices include volatile memories such as DRAM (dynamic random access memory) and SRAM (static random access memory), and nonvolatile memories. All data stored in volatile memory disappears when the power is turned off. However, data stored in nonvolatile memory does not disappear even when the power is turned off. A typical non-volatile semiconductor memory device is PROM (pr
o g rammable read only
Mem.

ry). FROM is a semiconductor memory device into which information can be written by the user. This FROM is an EEPROM (EEPROM) that can electrically erase written information and rewrite the information as many times as needed.
y erasable and pro g r
amma b 1 e ROM). An EEPROM in which data stored in all memory cells can be erased at once is called a flash EEPROM.

FIG. 3 is a schematic block diagram showing the basic configuration of a conventional flash EEPROM. Referring to FIG. 3, the flash EEFROM includes memory array 1. Low decoder 6
0. Y gate 70. and a column decoder 80.

The memory array 1 includes a plurality of memory cells MC arranged in a matrix in the row and two column directions.

Each memory cell MC is connected to a corresponding bit line 30 and word line 50 in memory array 1. Each memory cell MC has a FAMOS (floating gate) that can store charges in its floating gate.
e avalanche injection
MOS)) transistors are used.

FIG. 4 is a sectional view showing a FAMOS transistor structure. Referring to FIG. 4, the FAMOS) transistor is
Control gate 200 and floating gate 2
10 and an N-type region 220 formed on a P-type substrate 240.
and 230, and an insulating layer 250. The floating gate 210 has an N-type region 22 on a P-type substrate 240.
0 and N-type region 230, insulating layer 250
formed through. Control gate 200 is formed on floating gate 210 with insulating layer 250 interposed therebetween. Control gate 200 and floating gate 210 are both formed of polysilicon. The insulating layer 250 is formed of an oxide film such as 5i02.

The thickness of the oxide film 250 between the P-type substrate 240 and the floating gate 210 is usually about 100 Å, which is very thin. Control gate 200 is connected to the corresponding word line 50 in FIG. One of the two N-type regions 220 is connected to the corresponding bit line 30 in FIG. 3 as the drain of this MOS transistor.

The other N type region 230 serves as the source of this MOS transistor. It is connected to a source line 28 common to all memory cells MC in J. P-type substrate 2
40 is grounded.

During data writing, a high voltage pulse of 12V is applied to the control gate 200 and the drain 220 via the word line 50 and the bit line 30, respectively, while the source 2
30 is grounded via source line 28. drain 22
By applying a high voltage pulse to 0 and grounding the source 230, the drain 220 and the P-type substrate 240
Avalanche collapse occurs near the interface. As a result, in the depletion layer near the drain 220, free electrons (hot electrons) O with high energy and
A hole (■) corresponding to this electron is generated. The hole ■ flows to the grounded P-type substrate 240. On the other hand, since a high voltage pulse is also applied to the control gate 200, the generated hot electrons O are transferred to the control gate 200.
00, and is injected into the floating gate 210 through the thin oxide film 250 between the floating gate 210 and the P-type substrate 240.

The charges injected into the floating gate 210 cannot escape because the floating gate 210 is electrically insulated by the oxide film 250. Therefore, the electrons once injected into the floating gate 210 remain in the floating gate 210 even after the power is turned off.
From 0, it does not flow out for a long time and accumulates. A state in which electrons are accumulated in the floating gate 210 corresponds to data "0", and a state in which no electrons are accumulated in the floating gate 210 corresponds to data "1".

Therefore, the data stored in memory cell MC is retained even after the power is turned off. Now, floating gate 21
When electrons are accumulated at zero, the polarity between the source 230 and the drain 220 (that is, the channel region) shifts in the positive direction due to the electric field from the accumulated electrons. For this reason,
A negative polarity inversion layer is less likely to form in the channel region. Therefore, when electrons are accumulated in the floating gate 210, the gate voltage required to generate a channel in this MoS transistor (threshold voltage of this transistor) is higher than when electrons are not accumulated in the floating gate 210. Become. In other words, an inversion layer is not generated in the channel region unless a higher voltage is applied to the control gate 200 than when no electrons are stored in the floating gate 210.

When stored data is erased, a high voltage is applied to the source 230 via the source line 28, while the control gate 200 is grounded via the word line 50. This allows floating gate 210 and source 230 to
A high electric field is applied with the source 230 on the high potential side. As a result, a tunnel phenomenon occurs in the oxide film 250 that insulates the floating gate 210 and the source 230, and a current (tunnel current) flows between the floating gate 210 and the source 230. That is, an oxide film 2 is formed from the floating gate 210 to the source 230.
Electrons flow out through 50. As a result, the electrons accumulated in the floating gate 210 are removed, and the threshold voltage of this MOS transistor is lowered. As shown in FIG. 3, since the source line 28 is commonly connected to the source of each memory cell MC, the data stored in all memory cells MC in the memory array 1 in FIG. 3 is erased all at once. Ru.

When reading data, a power supply voltage (usually 5V) and a relatively similar voltage are applied to the control gate 200 and the drain 220 via the corresponding word line 50 and bit line 30, respectively, while the source 230 is connected to the source line 28. grounded through. floating gate 21
If no electrons are stored in 0 (memory data is “1”)
Since the threshold voltage of this MOS transistor is low, a channel is generated between the source 230 and the drain 220 by the power supply voltage applied to the control gate 200. However, if electrons are accumulated in the floating gate 210 (if the stored data is 0''), the threshold voltage of this MOS transistor is high, so even if the power supply voltage is applied to the control gate 200, the source 230 - No channel is generated between the drains 220. Therefore, the MOS transistors constituting the memory cells whose stored data is "1" are in the N state when data is read, and a current flows from the corresponding bit line 30 to the source line 28. However, since the MoS transistors constituting the memory cells in which the stored data is "0" are in the OFF state even when data continues to flow, no current flows from the corresponding bit line 30 to the source line 28. Reading 8
Sometimes, a sense amplifier detects whether a current flows through a bit line corresponding to a memory cell from which data is to be read. Based on the results of this detection, the stored data is
It is determined whether it is 1'' or 0''.

However, if the potential applied to the bit line 30 is too high when data is continuously generated, a high electric field is applied to the oxide film 250 between the floating gate 210 and the drain 220, so that the electrons accumulated in the floating gate 210 are transferred to the drain 220 side. It goes through. Therefore, bit line 30
The potential applied to is about 1 to 2V. therefore,
When reading data, a small current flows through a memory cell whose stored data is "1". Therefore, a current sense amplifier is used to detect this current.

Referring again to FIG. 3, address input terminals AO to AK receive address signals applied from the outside. The address signal is a signal instructing which of the memory cells MC in memory array 1 data is to be successively written or data is to be written.

Address buffer 100 buffers the applied address signal and provides it to row decoder 60 and column decoder 80.

The human output buffer 110 is connected to an input/output terminal I/Oo=I/ON for receiving input data and a-capacity data. The human output buffer 110 has an input/output terminal l1
Write data externally applied to 0o-IloN is applied to the write circuit 90. Furthermore, the crowd buffer 110 is
The data output from the sense amplifier 120 is led out to the 8 input terminals I/Oo''=I/Os as successive data.

Write circuit 90 applies a voltage to Y gate 70 according to write data applied from output buffer 110 . The sense amplifier 120 detects the output of the Y gate 70 and supplies a signal voltage corresponding to data "0" or "1" to the input/output buffer 7110 as read data according to the detection result.

Row decoder 60 responds to address signals from address buffer 100 to
Select one of 0. Column decoder 8
0 selects any one of the bit lines 30 in the memory array 1 in response to an address signal from the address buffer 100.

The control circuit 140 includes Y gates 70 . column decoder 80
．． Write circuit 90. Address buffer 100, human output buffer 110. and sense amplifier 120 so that they operate according to each mode.

A high voltage vPP is applied to the terminal TPP from the outside. A normal level power supply voltage Vcc is externally applied to the terminal Tcc. The switch circuit 600 has terminals Tpp and T
High voltage VPP and power supply voltage V given to cc respectively
. Either one of C is selectively output to a predetermined circuit section.

The switch circuit 600 is controlled by the control circuit 140 and receives high voltage VP from the terminal T'pp during data writing.
is given to the row decoder 60. Furthermore, the switch circuit 6
00 is controlled by control circuit 140 to apply power supply voltage VCC to row decoder 60 during data reading. Furthermore, the switch circuit 600 is controlled by the control circuit 140 to apply high voltage VPP to the source line switch 150 during data erasing.

During data writing, Y gate 70 applies a voltage applied from write circuit 90 to the bit line selected by column decoder 80 . Specifically, if the write data is "O", the Y gate 70 applies high voltage vPP to the selected bit line. If the write data is 1”, Y
Gate 70 holds the potential of the selected bit line at ground potential. When writing data, the row decoder 60 applies a high voltage v from the switch circuit 600 to the selected word line.
Apply pp. On the other hand, during data writing, the source line switch 150 applies the ground potential to the source line 28. Therefore, if the write data is "0", the floating gate of the memory transistor (selected memory transistor) located at the intersection of the word line selected by the row decoder 60 and the bit line selected by the column decoder 80 Electrons generated by avalanche collapse are injected only into 210. However, if the write data is "1", no electrons are injected into the floating gate 210 of the selected memory transistor because the control gate 200 is not boosted. When data continues to be output, the row decoder 60 applies the power supply voltage Vc from the switch circuit 600, which is lower than the high voltage Vpp, to the selected word line. During data writing, Y gate 70 applies a low voltage of 1 to 2 cm to the bit line selected by column decoder 8o. on the other hand,
When data is continuously written, the source line switch 150 applies the ground potential to the source line 28, similarly to when writing data.

Therefore, if the stored data of the selected memory transistor is "0", the selected bit line is connected to the source line 28 to the drain 220 . Current flows through the channel region and source 230.

If the stored data of the selected memory transistor is "1", the selected memory transistor is not turned on by the gate voltage of about 5V, so no current flows through the selected bit line.

Now, the Y gate 70 applies a power supply voltage to the selected bit line and electrically connects only the selected bit line to the sense amplifier 120.

This allows the sense amplifier 120 to detect the presence or absence of current flowing through the selected bit line.

When erasing data, Y gate 70 keeps all bit lines 30 in memory array 1 at a low potential (ground potential).

When erasing data, row decoder 60 applies a ground potential to all word lines 50 in memory array 1 .

When erasing data, the source line switch 150 converts the high voltage VPP from the switch circuit 600 into a pulse signal and applies it to the source line 28 . Therefore, when erasing data, a tunnel phenomenon occurs in each of all memory cells MC in the memory array 1, and the stored data becomes "0".
” Floating gate 2 of the memory transistor
The electrons stored in the floating gate 21
removed from 0. Therefore, at the end of data erasing, the stored data in all memory cells MC in memory array 1 becomes "1".

In the following description, it is assumed that the power supply potential and the ground potential correspond to logic levels "H'" and "L", respectively.

In this way, in EEFROM, when erasing data, the control gate 200 and source 23 of the memory transistor are
Data erasure is achieved by applying a high voltage between the floating gate 210 and the source 230, forcing electrons to tunnel from the floating gate 210 to the source 230. will be held. Therefore, the amount of electrons extracted from the floating gate 210 is
The magnitude of the high voltage applied to the floating gate 8, the time for applying the high voltage (pulse width of the high voltage pulse), and the floating gate 210.
The thickness of the oxide film 250 between the floating gate 210 and the control gate 200 varies depending on the thickness of the oxide film 250 between the floating gate 210 and the control gate 200, and the like.

On the other hand, manufacturing variations occur in the memory transistors constituting the memory array 1. Due to this variation,
The thickness of the oxide film 250, the shapes of the control gate 200 and floating gate 210, the length of the channel region, etc. are not completely the same in all memory transistors.

Due to various factors such as manufacturing variations between memory transistors and actual circuit configurations, it is not possible to erase data stored in all memory cells MC in memory array 1 at the same time using the above-mentioned batch erase. It is actually difficult to set it to "0". In other words, the stored data is '0'
In some of the memory transistors, only the accumulated electrons are completely removed from the floating gate 210 by the high voltage applied during bulk erase; The high voltage pulse causes more electrons than those accumulated during data writing to be extracted from the floating gate 210.

The phenomenon in which electrons are excessively extracted from the floating gate, as in the latter case, is called overerasure or overerasure.

When over-erasing occurs, the floating gate 210 becomes positively charged, so that a negative polarity inversion layer is generated between the source 230 and the drain 220. This means that this memory transistor is in the ON state no matter what potential above 07 is applied to the control gate 200. As a result, current flows through the bit line corresponding to this memory transistor even though it is in a non-selected state during data reading. Therefore, when a memory cell connected to the same bit line as the over-erased memory transistor is selected, the read data becomes "1" even if the stored data of the selected memory transistor is "0". . In addition, when writing data, if an attempt is made to write data "0" to an over-erased memory cell or a memory cell connected to the same bit line as the over-erased memory cell, the selected memory cell Electrons generated by avalanche collapse leak to the bit line as a channel current of the overerased memory cell. Therefore, sufficient electrons are not injected into the floating gate 210 of the selected memory cell. Therefore, if there is an overerased memory cell, the write characteristics during data writing will deteriorate, and furthermore, it will become impossible to write. In this manner, over-erasing inverts the polarity of the threshold voltage of the memory transistor to negative, thereby causing problems in subsequent data succession and data writing.

Therefore, in order to prevent such over-erasing, the following method is currently used. That is, the pulse width of the high-voltage pulse (hereinafter referred to as an erase pulse) applied to the source line 28 for erasing data is shortened, and each time an erase pulse with a short pulse width is applied to the source line 28, the memory is The storage data of all the memory cells in the array 1 are read out to check whether the storage data of all the memory cells MC in the memory array are all "1". and,
If there is even one memory cell whose stored data is not "1", the erase pulse with the short pulse width is applied to the source line 28 again. The process of confirming whether the data stored in the memory cell has become "1" by applying the erase pulse to the source line 28, that is, whether the data stored in the memory cell has been completely erased, is called erase verification. . Such erase verify and application of the erase pulse to the source line 28 erases all memory cells M in the memory array 1.
This process is repeated until data erasure for C is completed. Flash EEPROMs that prevent over-erasing in this way are
For example, rlssec Digest of Technical Papers (1990) J, pp. 60-61 and “
IEICE Technical Research Report May 21, 1990, pp. 73-77.

[Problems to be Solved by the Invention] Before data erasure is performed, electrons are injected into the floating gate of the memory cell transistor. Therefore, during data erasing, the floating gate potential of the memory cell transistor is shifted to the negative side. For this reason, referring to FIG. 4, when erasing data, the source 230
Even if the voltage applied to the floating gate 210 is about 12 V, a very large electric field is actually induced in the oxide film 250 between the floating gate 210 and the source 230. Therefore, even if high voltages v and P for erasing data are applied to the source 230 as a pulse signal with a short pulse width of about 10 m5 ec, electrons may be excessively extracted from the floating gate 210 (overerasing). Next, this phenomenon will be explained in more detail.

FIG. 5 shows the control gate 200. Floating gate 210. Drain 220. 3 is an equivalent circuit diagram of a memory transistor showing a capacitive coupling relationship between a source 230 and a substrate 240. FIG. In the figure, capacitor CCF
I CD I Cc g and Cs are the capacitance between the control gate 200 and the floating gate 210, the capacitance between the floating gate 210 and the drain 220, and the floating gate 210, respectively.
and the capacitance between the substrate 240 and the floating gate 21
0 and source 230. therefore,
Nodes Nl, N2. N3. N4. N5 are control gates 200 . floating gate 210, source 230. Substrate 240. and drain 220. Here, the amount of charge accumulated in the floating gate 210 is expressed as QFG, and the amount of charge accumulated in the control gate 210 is expressed as QFG.
The potential applied to the drain 220 is expressed as vG, the potential of the drain 220 is expressed as Vo, the potential of the source 230 is expressed as vs, and the channel region between the drain 220 and the source 230 (
When the potential of the drain 220 of the substrate 240 and the portion corresponding to the source ζ230 is expressed by vo, the potential of the floating gate 210 (the potential of the node N2) Vyc is expressed by the following equation.

In addition, in the above formula, Cc p + CD I C
c + and C9 represent the capacitance value of capacitor Cap, capacitor CD, capacitor C0, and capacitor C8 in FIG. 5, respectively. Further, CToTAL represents the sum of these capacitances, that is, Cc p +cD+Cc +cs. On the other hand, the coupling ratio kc is the control gate 20
0 and the floating gate 210 (control gate) 200. Floating gate 210. Drain 220. Source 230. It is defined as the ratio to the total capacitance CTOTAL between the substrates 240 and the substrate 240 by the following equation.

kc=COF/CTOTAL'...(2)
Also, the threshold value of the floating gate 210 of this memory transistor as seen from the control gate 200 is
The amount of change ΔVTH due to the accumulation of electrons is expressed by the following equation.

ΔVt M = QF c / Cc F − (3)
When erasing data, control game) 200° drain 220. and the substrate 240 is grounded, and the source 2
Since high voltage VPP is applied to 30, vG=VC=VD=0■ in the above equation (1).

Vs=Vpp. Therefore, the potential VFG of the floating gate has a coupling ratio k according to the above equations (1) to (3). It is expressed as in the following equation using the amount of change in threshold value ΔvTH.

VFG=C8VPP/CTOTAL kcΔVT)I
(4) Therefore, the potential difference between the floating gate 210 and the source 230 is expressed by the following equation.

(I C5/CT OT A L ) Vp p +
kcΔVTM (5) The magnitude of the electric field induced between the floating gate 210 and the source 230 is proportional to the potential difference between the floating gate 210 and the source 230, and is proportional to the thickness of the oxide film 250 between the floating gate 210 and the source 230. is inversely proportional to. Therefore, the magnitude of this electric field is as follows: the thickness of the oxide film between the floating gate 210 and the substrate 240 is 100 mm, the amount of threshold change ΔvTH is 5 mm, the coupling ratio is 0 and 0.6, and the C8/CTOTAL is If the value is 0.1 and high voltage Vpp is 12V, 13.8M
V/cm. In other words, when erasing data, the oxide film of the value of the floating gate 210 and the source 230 has 13
．． A very strong electric field of 8 MV/cm is induced. This strong electric field causes a tunneling phenomenon and electrons are extracted from the floating gate 210.

Generally, in order to cause a tunneling phenomenon to extract electrons accumulated in the floating gate 210 to the source 230, the floating gate 210 and the source 230 must be connected to each other.
An electric field of IOMV/cm or more may be induced in the oxide film 250 between the two. However, currently, the external power supply for driving semiconductor devices that operates at the next highest voltage after 5V is a 12V power supply.

On the other hand, in a flash EEFROM, the total amount of current flowing through the bit line during data writing is about 1 mA to 5 mA, so it is difficult to generate a high voltage for data writing inside the chip. That is, when generating high voltage inside a chip, a high voltage generating circuit such as a charge pump is used that derives high voltage by sequentially charging a plurality of capacitors over time. However, such a high voltage generating circuit cannot supply a current of 1 mA to 5 mA required for data writing. For example, the magnitude of current I that can be supplied by a charge pump is determined by the product of the capacitance value C of the capacitor used and the charging frequency f of the capacitor. The capacitance value C is 10 pF, and the charging frequency f is 10 pF.
Even at MHz, the charge pump supply current I is 10
Very small at 0μA. Therefore, the high voltage required for data erasing and data writing needs to be supplied from an external power supply.

For these reasons, a high voltage of 12V is currently used to erase data. As a result, during data erasing, an unnecessarily strong electric field (13, 8
MV/cm), which increases the risk of over-erasing.

Furthermore, when the gate voltage is 0 in an N-channel MOS transistor, a phenomenon called band-to-band tunneling occurs in the overlapping region of the gate and drain diffusion regions. This phenomenon also occurs in the overlapping region of the gate and source diffusion region when the source potential is high. Band-to-band tunneling occurs because the surfaces of the N-type drain and source diffusion regions are in a deep depletion state because the gate voltage is 0. These N
When the surface of the type diffusion region enters a deep depletion state, the curve of the energy band at the boundary between the oxide film under the gate and the substrate becomes steep.

Therefore, electrons of the valence body tunnel into the conduction band in the N-type diffusion region. Holes generated at this time flow to the grounded substrate, while electrons tunneled into the conduction band gather in the N-type diffusion region. The current generated by holes flowing into the substrate becomes a leakage current of this N-channel MO3) transistor.

When erasing data, a high voltage is applied to the source 230 of the memory transistor and the control gate 200 is grounded, so that this interband tunneling phenomenon occurs.

Referring again to FIG. 4, when erasing data, the portion 2 near the source 230 of the interface between the substrate 240 and the oxide film 250 is
It is known that interband tunneling phenomenon occurs in 60. Since the substrate 240 is grounded, holes generated by this phenomenon flow as a leakage current toward the substrate 240, and electrons tunneled into the conduction band flow toward the source 230 together with the electrons extracted from the floating gate 210. Regarding the phenomenon of interband tunneling in such flash EEFROM, see J.

Chen, et al., “Subbrea
kdown drain leakage
current in MOSFET, “
IEEE Electron Device
1ett,,v.

1, EDL-8, pp. 515-517.1987, and H. Kume et al., “AFR
ASH-ERASE EEPROM CELL
WITHAN ASYMMETRIC5UOURCE
AND DRAIN 5TRUCTUR
E″ IEEE Tech, Dig, of IEDM1
987. 25. 8. pp, 560-563
etc. is stated. According to these documents, the leakage current caused by the interband tunneling phenomenon is about 10-8 A per memory transistor when the potential of the source 230 is about IOV'. Therefore, for IMbit flash EEPROM, 10
When data is erased by applying a high voltage pulse of v to the source 230, the leakage current generated during data erasing is 10 mA.
becomes. Such leakage current causes various problems such as chip heat generation due to increased power consumption and a drop in power supply voltage. Generally, the allowable range of such leakage current is as follows:
It is 0mA or less. However, as the capacity of semiconductor devices has increased in recent years, the number of memory transistors in flash EEPROMs has also been increasing.
The capacity of M is currently increasing to around 16Mbit.

For example, in the case of a 16 Mbit flash EEPROM, when data is erased using a high voltage pulse of 10 V, the leakage current during data erasing is 10 mAX16, that is, 160 mA, which greatly exceeds the allowable range. In reality, the voltage applied to the source 230 for data erasing is 1
Since it is 2V, the actual magnitude of the leakage current is even larger than this value. Given this current situation, it is necessary to reduce leakage current that occurs during data erasing as much as possible.

Further, in order to prevent over-erasing, the conventional improved flash EEPROM repeats a cycle of applying an erase pulse with a short pulse width to the memory array and then performing erase verify. Therefore, when a memory cell whose data has not been completely erased is detected by the erase verify operation, an erase pulse is applied again to all memory cells in the memory array. Therefore, the erase pulse applied again to the memory array works to remove the electrons accumulated in the floating gate during data writing in the memory transistors whose data has not yet been completely erased, but the erase pulse which has already completely erased the data In the erased memory transistor, the electrons that were originally present in the floating gate are pulled out from the floating gate. As a result, when data erasing for memory cells from which data is difficult to erase is completed, over-erasing occurs in memory cells from which data is easily erased.

The greater the variation in the ease with which data can be erased between the memory cells that make up the memory array, the greater the number of erase pulse applications required to completely erase data among the memory cells that make up the memory array 1. It varies. The erase pulse that is re-applied to completely erase the data in the memory cell detected by erase verify cannot completely erase the data on the memory cell whose data is more difficult to erase than the detected memory cell. There are cases. In this case, when this memory cell whose data is difficult to erase is detected in the next erase verify, the erase pulse is applied again to all the memory cells in the memory array. Therefore, the greater the dispersion in ease of data erasure among the memory cells that make up the memory array, the more data will be erased from the memory cell that is least likely to be erased (the data in all memory cells in the memory array will be erased). The number of times an erase pulse is applied to the memory array (until it is completely erased) increases. Therefore, there is a high possibility that many memory cells will be over-erased when the erase operation is completed.

Between memory cells configuring one memory array,
As mentioned above, there are variations in the ease with which data can be erased.
This is due to various manufacturing and circuit configuration factors. Such variations increase as the number of memory cells forming one memory array increases. Therefore, the recent increase in the capacity of semiconductor memory devices, that is, the increase in the number of bits, makes the above-mentioned problems more pronounced.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and provide a nonvolatile semiconductor memory device that consumes less power when erasing data and has less risk of over-erasing.

[Means for Solving the Problems] In order to achieve the above objects, a nonvolatile semiconductor memory device according to the present invention uses a field effect semiconductor element including a floating gate and first and second impurity diffusion regions. Data is written by injecting charges into the floating gate from near the first impurity diffusion region by avalanche collapse, and the injected charges are transferred from the floating gate by a tunneling phenomenon. A nonvolatile semiconductor memory device in which data is erased by removing impurities into a second diffusion region, wherein a high voltage is applied to each of the first and second impurity diffusion regions of a field effect semiconductor element when erasing data. Have the means.

[Operation] Since the nonvolatile semiconductor memory device according to the present invention is configured as described above, a high voltage is applied not only to the second impurity diffusion region but also to the first impurity diffusion region when erasing data. Therefore, since the potential of the first impurity diffusion region is set high during data erasing, the potential of the floating gate is higher than that of the prior art. As a result, the potential difference between the floating gate and the second impurity diffusion region during data erasing becomes smaller than before, so the strength of the electric field applied between the floating gate and the second impurity diffusion region is reduced compared to before. .

[Embodiment] FIG. 1 is a schematic block diagram showing the configuration of the main parts of a flash EEPROM according to an embodiment of the present invention.

Referring to FIG. 1, this flash EEPROM, unlike the conventional one shown in FIG. 3, includes a bit line high voltage switch 400 provided between memory array 1 and source line switch 150; and a booster circuit 500 provided between the switch circuit 600 and the switch circuit 600 .

Except for the bit line high voltage switch 400 and the booster circuit 500 (the configuration and operation of the other functional blocks are similar to those in the conventional flash EEPROM shown in FIG. The high voltages v and P output at the same time are applied not only to the source line switch 150 but also to the booster circuit 500.

Hereinafter, with reference to FIG. 2, the features of this embodiment are as follows.
The circuit operation during data erasing of this flash EEFROM will be mainly explained. FIG. 2 shows the internal configurations of the memory array 1, the Y gate 70, and the bit line high voltage switch 400, as well as the internal configurations of the memory array 1, the Y gate 70, and the bit line high voltage switch 400, taking as an example the case where the memory array 1 includes nine memory transistors arranged in a matrix of 3 rows and 3 columns. FIG. 3 is a circuit diagram showing a connection relationship between the device and peripheral circuits.

First, before explaining the operation, the memory array 1°Y gate 70. And the internal configuration of bit line high voltage switch 400 will be explained.

Referring to FIG. 2, memory array 1 includes row decoder 6
Word lines WL1 to WL3 connected to 0 and Y gate 7
Bit lines BLI to BL3 connected to 0 and word line W
It includes memory transistors MC provided corresponding to each of the intersections of LI to WL3 and bit lines BL1 to BL3.

Memory transistor MC has a structure shown in FIG.

The sources of all memory transistors MC are commonly connected to a source line 28 that is connected to a source line switch 150. The Y gate 70 is connected to the ■10 line 27, which is connected to the write circuit 90 and the sense amplifier 120, and the I10 line 27.
and N-channel MOS transistors TR1-TR3 provided as transfer gates between each of bit lines BLI-BL3. Transistors TRI~TR3
The gates of are connected to the column decoder 80 via mutually different connection lines Y1 to Y3. In this way, the connection line Y1
~Y3 are provided in one-to-one correspondence with bit lines BLI~BL3.

Row decoder 60 selectively outputs high voltage VPP to any one of word lines WLI to WL3 in memory array 1 in response to an applied address signal. Column decoder 80 selectively applies an "H" level voltage to only one of connection lines Y1 to Y3 in Y gate 70 in response to an applied address signal.

As a result, among the transfer gates TRI to TR3, only those provided corresponding to the selected connection line are turned on, and only those corresponding to the selected connection line among the bit lines BLI to BL3 are connected to the I10 line. It is electrically connected to 27.

The write circuit 90 is controlled by the control circuit 140, and
When writing data, high voltage VPP is applied to the I10 line 27. On the other hand, the I10 line 27 is electrically connected only to the bit line 2 selected by the column decoder 80. Therefore, the high voltage VPP applied to the I10 line 27 is applied only to the selected bit line (one of BLI to BL3). The source line switch 150 connects the source line 28
Apply ground potential to

As a result of this circuit operation, during data writing, electrons generated by avalanche collapse are injected into the floating gate of only one memory transistor corresponding to an external address signal among the memory transistors MC in the memory array 1. be done.

The row decoder 60 is controlled by the control circuit 140 to read the word line WL1 in the memory array 1 during data reading.
- Supply the power supply voltage of 5V from the switch circuit 600 to only one word line of WL3 that corresponds to the address signal from the address buffer 100, and keep the potentials of the other word lines at "L" level. do. As a result, in the memory array 1, 5V is applied to the control gates of all memory transistors connected to the selected word line. The column decoder 80 is controlled by the control circuit 140 to apply an "H" level voltage only to the connection lines Y1 to Y3 in the Y gate 70 that correspond to the address signal applied from the address buffer 100, and to The potential of the connecting line is held at the "L" level.

As a result, in the Y gate 70, only one of the transfer gates TRI to TR3 provided corresponding to the selected connection line is turned on. As a result, only the selected bit line among the bit lines BLI to BL3 is electrically connected to the I10 line 27. Further, the source line switch 150 grounds the source line 28 when the high voltage Vpp is not applied from the switch circuit 600. Therefore, during erase verification, 5V and OV are applied to the control gate and source of the selected memory transistor in memory array 1, respectively, and only the current flowing to the bit line connected to the selected memory transistor can be detected. becomes.

If electrons are not accumulated in the floating gate of the selected memory transistor, that is, if the threshold voltage of the selected memory transistor is lower than a predetermined value, the selected memory transistor is The memory transistor becomes conductive. Therefore, current flows from the I10 line 27 to the source line 28 via the selected transfer gate and the selected bit line. The predetermined value is set to an average threshold voltage of memory transistors to which no data is written.

Therefore, if no electrons are stored in the floating gate of the selected memory transistor, current flows through the selected bit line. However, if electrons are accumulated in the floating gate of the selected memory transistor, the threshold value of the selected memory transistor will not fall to the predetermined value. Therefore, the selected memory transistor is not rendered conductive by the 5V gate voltage applied from the row decoder 60, and no current flows through the selected bit line.

The bit line high voltage switch 400 connects bit lines BL1 to BL.
3 and N-channel MOS transistors GSWI to GSW3, respectively. transistor G
SW1 to GSW3 are the corresponding bit lines BLI to BLI, respectively.
The drain is connected to L3. Transistor GSWI~
The sources of GSW3 are commonly connected to source line 28.

The output voltage ER8 of the booster circuit 500 is commonly applied to the gates of the transistors GSWI to GSW3.

The boost circuit 500 switches the switch circuit 600 when erasing data.
The high voltage Vp p (12V) applied from the bit line high voltage switch 400 is boosted to a predetermined level, for example, about 13V to 14V.

The bit line high voltage switch applies high voltage V1 . Apply a voltage approximately equal to .

When erasing data, the booster circuit 500 outputs a voltage vPP10a that is slightly higher than the high voltage Vpp.

As a result, the gate potential of each of the transistors GSWI to GSW3 in the bit line high voltage switch 400 is set to V.
It is fixed at PP+α. On the other hand, high voltage VPP is applied to the source line 28 from the source line switch 150. Therefore, high voltage VPP is applied to the sources of each of transistors GSW1 to GSW3 via source line 28. Therefore, transistors GSWI-GSW3 each become conductive, and apply a voltage lower than gate potential VPP+α by the threshold voltage to corresponding bit lines BLI-BL3. The a voltage ER3 of the booster circuit 500 is set so that the boost amount α has a value approximately equal to the threshold voltages of the transistors GSWI to GSW3. By setting the output voltage ER3 of the booster circuit 500 in this manner, the voltages applied to the bit lines BLI to BL3 during data erasing become approximately equal to the high voltage Vpp applied to the source line 28.

On the other hand, row decoder 60 applies an "L" level potential to all word lines WLI to WL3. Further, the column decoder 80 applies a potential at the "L" level to the connection lines Y1-Y3 to make all the transfer gates TR1-TR3 non-conductive. Therefore, in this embodiment, all memory transistors MC in memory array 1 are
A high voltage VPP is applied to the drain and source of. The control gates of these memory transistors MC are grounded as before.

The floating gate potential VFG of the memory transistor MC during data erasing is expressed by the equation (1) shown above. Conventionally, the drain potential VD of the memory transistor MC during data erasing was OV. However, in this embodiment, since VD=V, P, the floating gate potential (Fo) of the memory transistor MC is higher than that of the conventional one and is expressed by the following equation.

[Vp (Co +Cs) +QF
a /CT OTAL (6) Therefore, the potential difference V5-V,0 between the floating gate and the source of the memory transistor MC becomes smaller than that in the conventional case during data erasing. The potential difference (1), -2 (F6) between the floating gate and the source of the memory transistor MC is expressed by the following equation using equations (2), (3), and (6).

VPP [1 (, CD+C8)/CTOTAL co+kc
ΔvTH... (7) On the other hand, the strength of the electric field applied to the oxide film between the floating gate and the source of the memory transistor is proportional to the potential difference VS VFG between the floating gate and the source. Inversely proportional to thickness. Therefore, since the potential difference between the floating gate and the source is smaller than before, the strength of the electric field applied to the oxide film between the floating gate and the source is more relaxed than before. Specifically, a high voltage 1 is applied to the drain of the memory transistor MC while maintaining the structure of the memory transistor MC as before.
When 2V is applied, the strength of the electric field applied to the oxide film between the floating gate and source of memory transistor MC is relaxed to about IOMV/cm. That is, the strength of the electric field applied between the floating gate and source of memory transistor MC is relaxed to the smallest value that can cause a tunneling phenomenon for erasing data. Therefore, according to this embodiment, the risk of over-erasing occurring in the memory transistors MC in the memory array 1 is significantly reduced.

In this embodiment, when erasing data, the potential of all bit lines in the memory array 1 is the same as that of the source line 28. However, the voltage applied to the drain of the memory transistor MC during data erasing does not necessarily have to be the same as the voltage VPP applied to the source of the memory transistor MC. That is, when erasing data, an external high voltage VPP may be directly applied to the gates of transistors GSWI to GSW3 of the bit line high voltage switch 400, or a voltage lower than the external high voltages 1 and 2 may be applied. In such a case, a high voltage at a lower level than in the above embodiment is applied to the drain of the memory transistor MC, but the floating gate potential VFO of the memory transistor MC is still higher than the conventional one (because it becomes higher than that in the above embodiment). Almost the same effect can be obtained.

Note that the method of raising the potential level of all bit lines in memory array 1 during data erasing is not limited to the method in the above embodiment. For example, in FIG. 2, transistors GSWI to GSW3 may be removed, all output voltages of column decoder 80 may be boosted, and high voltage may be applied from write circuit 90 to I10 line 27 during data erasing. According to this method, transfer gates TRI to TR3 are all rendered conductive during data erasing, so the high voltage applied from the write circuit 90 to the I10 line 27 is applied to all bit lines BLI to BL in the memory array 1.
given to 3.

[Effects of the Invention] As described above, according to the present invention, when erasing data, an externally applied high voltage is applied to the source of the memory transistor, and at the same time, the same level of externally applied high voltage is applied to the drain of the memory transistor. A high pressure of a level of is applied. Therefore, the strength of the electric field applied between the floating gate and the source of the memory transistor is reduced compared to the prior art.

As a result, the risk of over-erasing occurring during data erasing is greatly reduced, making it possible to realize stable data erasing.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the configuration of the main parts of a flash EEPROM according to embodiments of the present invention, and FIG. 2 shows a memory array and a Y gate in FIG. 1. 3 is a schematic block diagram showing the structure of the main parts of a conventional flash EFPROM, and FIG. 4 shows the structure of a memory transistor in the conventional and embodiments. The cross-sectional view shown in FIG. 5 is an equivalent circuit diagram showing the overall capacitance relationship within the memory transistor. In the figure, 1 is a memory array, 7o is a Y gate, 60
8o is a row decoder, 8o is a column decoder, 90 is a write circuit, 120 is a sense amplifier, 150 is a source line switch, 400 is a bit line high voltage switch, and 500 is a booster circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Tpp, Tcc 婢J MC〆7゛）Death 1 and 30 Bee! Toki 1 28 ° North Chibori 3 507-Do 揉夷 27 ) Figure 5 c Voluntary amendment to the procedure) Display of the September 5, 1991 case 1990 Patent Application No. 158362 Person amending the name of the invention Case and Related Address Name Representative Non-volatile semiconductor memory device

Claims (1)

Claims: A plurality of memory cells are provided, each of the memory cells includes a field effect semiconductor element having a floating gate, and first and second impurity diffusion regions; Data writing is performed by injecting charges into the floating gate from near the impurity diffusion region, and the injected charges are removed from the floating gate to the second impurity diffusion region by tunneling. A nonvolatile semiconductor memory device in which data is erased by: further comprising means for applying a high voltage to the first and second impurity diffusion regions of each of the field effect semiconductor elements during data erasing.