JPH0447714A - phase synchronizer - Google Patents

Abstract

PURPOSE:To reduce the synchronization lock time by synchronizing an input signal with an oscillation signal in phase when a phase difference between the input signal and the oscillation signal is a prescribed value or over and by inverting the oscillation signal from a voltage controlled oscillator means so as to synchronize the input signal with the oscillating signal in opposite phase when the phase difference between the input signal and the oscillation signal is a prescribed value or below. CONSTITUTION:The phase locked loop is provided with a voltage controlled oscillator means 3, a phase difference discrimination means, an inversion means and a phase comparison control means comparing a phase of an output signal of the inversion means with a phase of an input signal so as to control the voltage controlled oscillator means 3. When a phase difference between the input signal and the oscillation signal is a prescribed value or over, the input signal and the oscillating signal are synchronized in opposite phase, and when a phase difference between the input signal and the oscillation signal is a prescribed value or below, the input signal and the oscillating signal are synchronized in phase. However, when the input signal and the oscillating signal are synchronized in opposite phase, the inverting signal of the voltage controlled oscillator means 3 is outputted. Thus, the maximum synchronization lock time is reduced to nearly a half at most without varying the integration time constant and the phase control variable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase synchronization device that generates an output signal that is in phase with an input signal.

BACKGROUND OF THE INVENTION Phase synchronizers have been an essential component of transmitters and receivers, facsimile machines, and the like.

A conventional digital phase synchronization device will be described below.

FIG. 4 is a block diagram of a conventional digital phase synchronizer. In Figure 4, 1 is a phase comparator that compares the phases of the input clock and output clock, 2 is a loop filter that integrates the output of phase comparator 1, and 3 is a digital voltage controlled oscillator that is controlled by the output signal of loop filter 2. has been done.

The operation of the digital phase synchronization device configured as described above will be explained below.

The phase of the output clock with respect to the input clock is compared by a phase comparator 1 and outputted to the loop filter 2 as phase lead or lag information. Loop filter 2 integrates the output signal of phase comparator 1 and controls digital voltage controlled oscillator 3 based on the integration result. The digital voltage controlled oscillator 3 synchronizes the phases of the input clock and output clock based on this control signal.

Regarding the above operation, the synchronization pull-in process when the phases of the input clock and the output clock have a relationship as shown in FIG. 6 will be explained.

First, as shown in Figure 5 @), the phase of the output clock with respect to the input clock is 180 at time 1 = 10.
If the phase comparator 1 is ahead by a value slightly smaller than the degree, the output of the phase comparator 1 outputs an H signal. When this state continues for a time corresponding to the specific number of integrals of the loop filter 2, the loop filter 2 outputs a control signal to the digital voltage controlled oscillator 3 to delay the phase. As a result, the phase difference between the output clock and the input clock is reduced as shown in FIG. 1=11. Repeat this operation one after another,
At time t==t4, the output clock is synchronized with the input clock.

Next, as shown in FIG. 6(b), the phase of the output clock with respect to the input clock is 18 at time 1==10.
If the delay is a value slightly smaller than 0 degrees, the phase comparator 1 outputs an L signal. When this state continues for a period of time corresponding to the integration time constant of the loop filter 2, the loop filter 2 outputs a control signal to the digital voltage controlled oscillator 3 to advance the phase. As a result, the phase difference between the output clock and the input clock is reduced as shown at time 1=11. Repeat this operation sequentially t = t 4
The output clock is synchronized with the input clock.

This maximum synchronization pull-in time is expressed with the elapsed time of the synchronization pull-in process on the horizontal axis and the phase difference between the input clock and the output clock on the vertical axis, as shown in Figure 6. Time is proportional and the phase difference approaches 0 degrees.

The important performance of this digital phase synchronized circuit is the stability of the synchronized state and the synchronization pull-in time.

To improve the synchronization state stability, increase the integration time constant of the loop filter or reduce the phase control amount of the digital voltage controlled oscillator.In order to shorten the synchronization pull-in time, increase the synchronization state stability. In order to improve this, the opposite approach is to reduce the integration time constant of the loop filter or to increase the phase control amount of the digital voltage controlled oscillator. In other words, improving the synchronization state stability and shortening the synchronization pull-in time have contradictory conditions.

A conventional improved digital phase synchronizer is shown in FIG. 7 as an example of a means for achieving both the improvement of the stability of the synchronization state and the shortening of the synchronization pull-in time.

In FIG. 7, numeral 1 is a phase comparator, and numeral 3 is a digital voltage controlled oscillator. Since these are the same as the configuration of the conventional example shown in FIG. 4, detailed explanation will be omitted. 10 is a 9o degree phase shifter that delays the phase of the output gate by 9o degrees, and 11 is a 9o degree phase shifter.
This is a phase shift comparator that compares the clock output from the 0 degree phase shifter 10 and the input clock. 12 is a 190 degree phase shifter that advances the phase of the output clock by 90 degrees, and 13 is a phase comparator that compares the clock output from the 100 degree phase shifter 12 with the input clock. 14 is a determiner and a phase comparator 11
Based on the outputs of and 13, it is determined whether the phase difference between the output clock and the input clock is greater than 90 degrees. 15
is a loop filter that integrates the output of the phase comparator 1, and the integration time constant can be changed depending on the output signal of the determiner 14.

The operation of the digital phase synchronization device configured as described above will be explained below.

The phase of the output clock with respect to the input clock is compared by the phase comparator 1, and at the same time, the phase difference is determined by the 90 degree phase shifter 1o, the phase comparator 11, the -90 degree phase shifter 12, the phase comparator 13, and the determiner 14. It is determined whether or not the angle is ±90 degrees or less. When the phase difference between the input clock and the output clock is ±90 degrees or less, the 90 degree phase comparator 10 and the phase comparator 1
For combination 1, the phase difference entering the phase comparator 11 is 0 degrees ~
The combination of the -90 degree phase shifter 12 and the phase comparator 13 means that the phase difference input to the phase comparator 13 is in the range of 1180 degrees to ○ degrees for the L signal, which is a phase delayed signal, because it is in the range of 180 degrees. Therefore, an H signal, which is a phase advance signal, is output. The determiner 14 determines that the phase difference is 90 degrees or less when the output signal of the phase comparator 11 is an L signal and the output signal of the phase comparator 13 is an H signal, and in other combinations, the phase difference is It is determined that the angle is thicker than 90 degrees. Loop filter 15
According to the output 1 word of the determiner 14, when the position A'' gap difference is 9o degrees or less, the integration time constant is set to τ1, and when the position A'' difference is smaller than 9o degrees, the time constant is set to be smaller than τ1 by υτ2. The digital voltage controlled oscillator 3 integrates the phase lead or phase lag information output from the phase comparator 1 according to this integral time constant, and controls the digital voltage controlled oscillator 3 based on the integration result. Synchronizes the phase of the output clock with the output clock.

Regarding the above operation, the synchronization pull-in process when the phases of the input clock and the output clock have a relationship as shown in FIG. 8 will be explained.

As shown in FIG. 8(a), when the phase of the output clock with respect to the input clock is ahead by a value slightly smaller than 180 degrees at time t-1o, the phase comparator 1 outputs the H signal at the same time. The integration time constant of the loop filter 16 becomes τ2 based on the determination signal of the determiner 14. When this state reaches a time line corresponding to the integral time constant τ2 of the loop filter 16, the loop filter 15 outputs a control signal to the digital voltage controlled oscillator 3 to delay its phase. As a result, the phase difference of the output clock with respect to the human clock is reduced, and the phase lead of the output clock with respect to the input clock at time t-11 becomes 90 degrees or less. At this time, determiner 1
4 changes, the loop filter 16 switches the integration time constant from τ2 to τ1, outputs a control signal to the digital voltage controlled oscillator 3 in the same way as above, and at time t-13, the output clock becomes the input clock. Synchronize. .

Next, as shown in FIG. 8(b), the phase of the output clock with respect to the input clock is 180 at time 1=10.
If the delay is a value slightly smaller than 1, the phase comparator 1 outputs an L signal, and at the same time, the judgment signal of the judgment unit 140 is used to set the integration time constant of the loop filter 15 to τ2 and output an output corresponding to the input clock at time t=t1. digital voltage controlled oscillator 3 until the clock phase difference becomes 90 degrees or less.
Outputs a control signal to. When the phase lead of the output clock with respect to the input clock becomes 90 degrees or less, a control signal is outputted to the digital voltage controlled oscillator 3 by setting the integration time constant of the loop filter 15 to τ1 according to the judgment signal of the judgment unit 14, and at time t=t3, the control signal is output to the digital voltage controlled oscillator 3.・Repeat this until the clock is synchronized with the input clock.

If this synchronization pull-in time is expressed with the elapsed time of the synchronization pull-in process on the horizontal axis and the phase difference between the input clock and the output clock on the vertical axis, the result will be as shown by the solid line in Figure 9, and the maximum synchronization pull-in time is shown by the dotted line. It can be seen that the maximum synchronization pull-in time in the conventional example shown in FIG. 4 is improved to t3 from t4, but the maximum phase difference remains at 180 degrees.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, in order to shorten the synchronization pull-in time, a circuit for determining whether the phase difference between input and output clocks is less than a predetermined phase difference, and an integration circuit for a loop filter are required. A time constant switching circuit is used, and the synchronization pull-in time can be shortened by lowering the value of the predetermined phase difference mentioned above or by reducing the integration time constant. Since there is a limit to reducing the integral time constant, there is also a limit to reducing the synchronous bowing time.

1. An object of the present invention is to solve the above-mentioned conventional problems, shorten the synchronization pull-in time, and provide a highly stable phase synchronization device.

Means for Solving the Problems In order to achieve the above object, the present invention provides voltage controlled oscillation means, and a phase difference between the phase of the oscillation signal outputted from the voltage controlled oscillation means and the input signal is greater than a predetermined value. a phase difference determining means for determining whether or not the output oscillation occurs; an inverting means for selecting whether or not to invert the signal of the output oscillation of the voltage controlled oscillation means according to an output of the phase difference determining means; and phase comparison control means for comparing the phases of input signals.

In the above configuration, the present invention inverts the oscillation signal of the voltage controlled oscillation means by the phase difference determination means and the inversion means when the phase difference between the input signal and the oscillation signal is larger than a predetermined value, so that the input signal and the oscillation signal are are synchronized in opposite phases to obtain an output inverted by the inverting means and in the same phase as the input, and when the phase difference between the input signal and the oscillation signal is less than a predetermined value, the input signal and the oscillation signal are synchronized in the same phase. By synchronizing them, the inverting means obtains an output that is not inverted and has the same phase as the input.

Embodiment FIG. 1 shows a block diagram of a digital phase synchronization circuit according to an embodiment of the present invention.

In FIG. 1, a phase comparator 1 and a loop filter 2 constitute a phase comparison control means, and 3 is a digital voltage controlled oscillator which is a voltage controlled oscillation means, which has the configuration of the conventional example shown in FIG. Since it is the same as , detailed explanation will be omitted. Inverter 4 inverts the output signal of digital voltage controlled oscillator 3 and selector 5 which selects either the output signal of voltage controlled oscillator 3 or the output signal of inverter 4 according to the output signal of phase comparator 6. constitutes a means. a 90 degree phase shifter 6 that delays the phase of the output signal of the digital voltage controlled oscillator 3 by 90 degrees;
The phase comparator 7 that compares the signal outputted from the input clock with the input clock constitutes a phase difference determining means.

The operation of the phase synchronized circuit configured as described above will be explained below.

The 90 degree phase shifter 6 and the phase comparator 7 reduce the phase difference between the input clock and the output signal of the digital voltage controlled oscillator 3 by 9.
It is determined whether or not it is greater than 0 degrees, and the determination result is output to the selector 5. When the phase difference between the input clock and the output signal of the digital voltage controlled oscillator 3 is greater than 90 degrees, the selector 5 selects the output signal of the impark 4;
When the voltage is below 30°C, the output of the digital voltage controlled oscillator 3 is selected. The phase comparator 1 compares the phases of the input clock and the output signal of the selector 5. Loop filter 2 integrates the output signal of phase comparator 1 and controls digital voltage controlled oscillator 3 based on the integration result. The digital voltage controlled oscillator 3 synchronizes the phases of the input clock and output clock based on this control signal.

First, as shown in FIG. 2(a), the output signal of the digital voltage controlled oscillator 3 with respect to the input clock is
7 If the phase is ahead by a value slightly larger than 90 degrees at time 1 = 10[, the phase comparator 1 outputs an H signal, and at the same time the selector 6 is impeded by the output signal H of the phase comparator 7. Select output signal 4. The output signal of the phase comparator 1 is input to the loop filter 2, and when this state continues for a time corresponding to the integration time constant, the loop filter 2 outputs a control signal to the digital voltage controlled oscillator 3 to advance the phase. As a result, the phase of the output signal of the digital voltage controlled oscillator 3 with respect to the human clock is synchronized with the inverted phase at time tt2. At this time, since the output signal of the phase comparator 7 is H, the selector 6 selects the output signal of the inverter 4, which is the inverted signal of the output of the digital voltage controlled oscillator 3, so the output clock is in phase with the input clock. Synchronize.

Next, as shown in FIG. 2(b), if the phase of the output signal of the digital voltage controlled oscillator 3 with respect to the input clock is ahead by a value slightly smaller than 9 degrees at time 1=10, then the phase comparator 1 At the same time as outputting the H signal 141, the selector 6 selects the output signal of the digital voltage controlled oscillator 3 based on the output signal of the phase comparator 7. The output signal of the phase comparator 1 is input to the loop filter 2, and when this state continues for a time corresponding to the integration time constant, the loop filter 2 outputs a control signal to the digital voltage controlled oscillator 3 to delay the phase. As a result, the phase of the output signal of the digital voltage controlled oscillator 3 with respect to the input clock is synchronized with the same phase at time t==t2. At this time, since the output signal of the phase comparator 7 is L, the selector 5 selects the output of the digital voltage controlled oscillator 3, and the output clock is synchronized with the input clock in phase.

Contrary to the synchronization pull-in process described above, when the output signal of the digital voltage controlled oscillator 3 is delayed in phase from the input clock in the initial state, it operates in the same way as when it is ahead of the input clock, and the phase difference is less than 90 degrees. When it is larger, the selector 5 selects the output of the impark 4 based on the output of the phase comparator 7, and the output signal of the digital voltage controlled oscillator 3 is synchronized with the input clock 15 and in opposite phase to the inverted signal of the digital voltage controlled oscillator 3. becomes the output clock, and when the phase difference is 90 degrees or less, the output signal of the digital voltage controlled oscillator 3 is synchronized with the input clock in the same phase, and the output signal of the digital voltage controlled oscillator 3 becomes the output clock, so the output clock is The clock also operates so that it is output in phase with the input clock.

When this maximum synchronization pull-in time is expressed with the elapsed time of the synchronization pull-in process on the horizontal axis and the phase difference between the input clock and the output clock on the vertical axis, it becomes as shown by the solid line in FIG. 3. Third
In the figure, 14 is the maximum synchronization pull-in time of the conventional digital phase synchronizer shown in FIG. 4, t3 is the maximum synchronization pull-in time of the improved digital phase synchronizer shown in FIG.
t2 represents the maximum synchronization pull-in time of the digital phase synchronizer of the present invention. As shown in FIG. 3, the maximum synchronization pull-in time has been improved from t4 to 12.

Although digital signals are used in the present invention, analog signals can also be used.

Further, the explanation has been made for the case where the phase of the 90 degree phase shifter 6 is +90 degrees, but when the phase is -90 degrees, the operation of the selector 5 may be considered as reversed.

Effects of the Invention As described above, the phase synchronization device of the present invention includes a voltage controlled oscillation means and a method for determining whether the phase of the oscillation signal outputted from the voltage controlled oscillation means and the phase of the input signal are larger than a predetermined value. a phase difference determining means for determining whether or not to invert the oscillation output signal of the voltage controlled oscillation means according to an output of the phase difference determining means; and a phase difference between the output signal of the inverting means and the input signal. The device is equipped with a phase comparison control means that controls the voltage controlled oscillation means by comparing the input signal and the oscillation signal, and when the phase difference between the input signal and the oscillation signal is larger than a predetermined value, the input signal and the oscillation signal are synchronized with opposite phases. , if the phase difference between the input signal and the oscillation signal is less than a predetermined value, the input signal and the oscillation signal are synchronized with the same phase, but if the input signal and the oscillation signal are synchronized with the opposite phase, the voltage control is performed. By outputting an inverted signal of the oscillation means output, the maximum synchronization pull-in time can be changed by changing the integral time constant, phase control amount, etc.
7. It has a great practical effect of being able to shorten the time by up to about half without any problems.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital phase synchronizer according to an embodiment of the present invention, Fig. 2 is a time chart diagram, Fig. 3 is a maximum synchronization pull-in time diagram, and Fig. 4 is a conventional digital phase synchronizer. , FIG. 6 is a time chart diagram, FIG. 6 is a maximum synchronization pull-in time diagram, FIG. 7 is a block diagram of an improved version of the conventional digital phase synchronizer, and FIG. 8 is a time chart diagram. FIG. 9 is also a maximum synchronization pull-in time diagram. 1.7... Phase comparator, 2... Loop filter, 3... Digital voltage controlled oscillator,
4...Inverter, 5...Selector,
6. River: 90 degree phase shifter. Name of agent: Patent attorney Shigetaka Awano.

Claims (1)

[Claims] voltage controlled oscillation means; phase difference determining means for determining whether a phase difference between the phase of the oscillation signal outputted from the voltage controlled oscillating means and the input signal is greater than a predetermined value; and an output of the phase difference determining means. inverting means for selecting whether or not to invert the oscillation output signal of the voltage controlled oscillation means according to the voltage controlled oscillation means; and controlling the phase of the voltage controlled oscillation means by comparing the phases of the output signal of the inverting means and the input signal. A phase synchronization device comprising a phase comparison control means.