JPH0447739A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate waveform distortion due to a low frequency cut-off characteristic by converting a data signal into a ternary level data signal at a level conversion circuit. CONSTITUTION:A middle level voltage is selected as an output voltage at no input of a data signal, a high level voltage is selected as an output voltage when a data signal is logical '1' and a low level voltage is selected as an output voltage when a data signal is logical '0'. That is, gate signals S3-S5 are formed from a data signal S1 and an enable signal S2. The gate signal S4 corresponds to the data signal S1 for non-signal period, the gate signal S3 corresponds to the data signal S1 for logical '1' periods and the gate signal S5 corresponds to the data signal S1 for logical '0' period. Thus, a middle voltage V2 is selected by the gate signal S4, a high level voltage V3 is selected by the gate signal S3 and a low level voltage V1 is selected by the gate signal S5. Thus, waveform distortion due to the low frequency cut-off characteristic is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level conversion circuit suitable for application to a PLL type modulation circuit used in mobile radio equipment such as a car telephone.

[Prior Art] Digital wireless communication systems are employed in mobile wireless devices such as car phones. Some of such mobile radio devices perform data modulation using a PLL type modulation circuit.

This modulation method directly modulates the voltage variable oscillator (VCO) that constitutes the PLL, and is often used in actual systems because it has excellent frequency stability and is easy to configure.

PLL type modulator 1 used in such mobile radio equipment
An example of 0 is shown in FIG.

Reference clock CLK supplied to terminal 12 is a frequency divider]
After being frequency-divided by 4 to 1/M, it is completely supplied to the phase comparator 16. Further, 18 indicates a voltage variable oscillator (VCO),
The output signal is divided into 1/N by a frequency divider 20, and is supplied to a phase comparator 16, where the phase is compared with the reference clock CLK, and the comparison output is extracted with a low-frequency component by a low-pass filter 22. The dough outputs the output signal So and outputs the output terminal 24.
is derived.

The output signal So is roughly supplied to VC018. A pulsed data signal (binary data) Sl used as a modulation signal is supplied to this VCO 18, and the oscillation frequency is controlled by this data signal S1 and output signal So.

By supplying the data signal S1, the output terminal 24
A pulsed output signal So is intermittently transmitted from the terminal.

That is, when a data signal S1 as shown in FIG. 8A is input, a pulse-like output signal SO as shown in FIG. 8B is obtained.

[Problem to be Solved by the Invention 1] However, in the PI-L type modulator 10, the oscillation frequency (center frequency) of the VCO 18 is always maintained in response to external disturbances. It has a region cutoff characteristic.

Therefore, the output signal SO obtained at the output terminal 24 has a waveform distortion due to a transient phenomenon having a low-frequency cutoff characteristic as shown in FIG. 8B. That is, the output signal SO has a waveform biased toward the positive side at the start of transmission.

In addition, the control voltage vs. oscillation frequency characteristic of VC018 is the 9th
It exhibits nonlinear characteristics as shown in the figure. For this reason, when frequency modulation is applied at a certain frequency, the frequency deviation Δf on the + side and the frequency deviation −Δf on the one side will be different.

Furthermore, this nonlinear characteristic itself differs depending on the VCO used. As an example is shown in FIG. 10, the control voltage for obtaining the same frequency deviation Δf is different from that in FIG. 9 due to the difference in characteristics.

Therefore, this invention solves these problems, and is a PI that can obtain a symmetrical modulation spectrum without being affected by the low cutoff characteristics.
, proposes a level conversion circuit that can be applied to an L-type modulation circuit.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a data signal that repeats at binary levels of logic "1" and "O" and a constant level for a period during which this data signal is obtained. In a level conversion circuit configured to convert an enable signal holding a value into a three-level data signal, the circuit includes an output voltage generating means for generating output voltages in three levels: high level, middle level, and low level, and output voltages in these three levels. a switching means for sequentially selecting one of the voltages; and a gate signal forming means for forming a gate signal for the switching means from the data signal and the enable signal; When the data signal is logic "1", the high voltage is selected as the output voltage, and when the logic is "O", the low voltage is selected as the output voltage, thereby converting the data signal into a ternary level. The gate signal forming means has a logic configuration so as to convert the data signal into a data signal, and the output voltages can be finely adjusted.

[Function] Logic level r1. ．． The data signal S1 having a binary level of ro is converted into a data signal S6 having a ternary level by a level conversion circuit 40.

This data signal S6 is formed as follows.

As shown in FIG. 4, data signal S1 and enable signal S2
Gate signals 83 to S5 are formed from the gate signals 83 to S5. Gate signal S
4 corresponds to a no-signal section of the data signal S1, the gate signal S3 corresponds to a logic "1" section, and the gate signal S
5 corresponds to the logical "O" interval.

Therefore, the intermediate voltage V2 is selected by the gate signal S4, the high voltage V3 is selected by the gate signal S3, and the low voltage V1 is selected by the gate signal S5.

With this, the binary data signal S1 can be converted into the ternary modulated signal S6.

Since the output voltages V1 to V3 can be varied, the center frequency f can be obtained by the output voltage 2, and Δ from this can be obtained by V3.
The individual output voltages V1~ V3 is adjusted.

[Embodiment] Next, a case where an example of the level conversion circuit according to the present invention is applied to the above-mentioned PLL type modulator will be described in detail with reference to the drawings.

FIG. 1 shows an example of a PLL modulator 10 to which the present invention is applied. A modulation signal S6 having a ternary level obtained from a modulation signal forming circuit 30 is supplied to the VCO] and 8.

The modulation signal forming circuit 30 is composed of an enable signal generating circuit 34 and a level converting circuit 40 as shown in the figure.
The data signal S1 from 2 is sent to the enable signal generation circuit 34.
supply.

From this, the transmission start timing and transmission end timing are detected from the pulsed data signal S1 as shown in FIG. 4A, and the rectangular waveform enable signal S2 shown in FIG. 4B is generated.

FIG. 2 shows an example of a level conversion circuit 40 according to the present invention.

In the figure, 60 is an output voltage generating means, and in this example, three variable resistors 41.4-2.4 are connected in series.
．． 3, one end of which is connected to the power supply voltage Vcc,
The other end is grounded.

Among the output voltages obtained from each, the highest voltage (high voltage) is set as V3, and the lowest voltage (low voltage)
Let Vl be Vl, and the voltage between them (medium voltage) be ■2.

The values of these output voltages V1 to V3 are determined by the variable resistors 41 to 43.
It can be adjusted by

These output voltages V1 to V3 are applied to the switches 52, 54 . ．． 56 to output terminal 57 from buffer 58 .

Further, 80 indicates a goo l-signal forming means. First, the terminal 32 is supplied with the data signal S1, and the terminal 36 is supplied with the enable signal S2.

The data signal S1 and the enable signal S2 are supplied to the AND circuit 48, and the gate signal S3 (fourth
(C) in the figure, the gate of the switch 52 is made conductive, and the high voltage V3 at that time is supplied to the connection point P.

Also, the enable signal S2 is passed through the inverter 46 to the gate signal S4. (D in the figure) is formed, which opens the switch 54 and supplies the intermediate voltage V2 to the connection point P.

Roughly speaking, the data signal S1 is supplied to the AND circuit 50 together with the enable signal S2 via the inverter 44, and its output gate signal S5 (E in the figure) opens the switch 56, and the low voltage V1 is supplied to the connection point P. be done.

Since the plurality of switches 52, 54, 56 are not opened at the same time, the voltage supplied to the connection point P is V3. V2. V
It is one of the potentials of l.

A filter or the like may be used instead of the buffer 58.

The above-mentioned AND circuit 48.50 and inverter 44.46
As an example, a 0MO8 logic circuit can be used, and its output level is assumed to be Vcc when it is "H" and the ground (GND) voltage when it is "L". In addition, switches 52, 54-. 56 is the gate signal 83~S5" I!
It shall be conductive when it is "I-" and cut off when it is "I-".

Next, the operation of this embodiment will be explained with reference to the truth table shown in FIG.

1 Enable - When "S2"l,"
Game i-Believing No. 1, No. 3, and 35 become L'', and the gate signal S
4 becomes "H". Therefore, the switch 54 becomes conductive, and the switches 52 and 56 become cut off.

As a result, the intermediate voltage V2 is output from the terminal 57, and this voltage is adjusted to the center frequency f by the variable resistor 42.

2 = Enable When 1 is "H" In this case, the gate signals S3 and S5 are in an inverse relationship, and the gate signal S4 is "L". Therefore, 2a data': ``When S1 is ``H'', in this case,
The gate signal s3 is "H", and the gate signal S4. S
5 is 'L''.

Therefore, the switch 52 is in a conductive state, and the switches 54 and 56 are in a conductive state.
is in a cut-off state, and high voltage V3 is output. Therefore, by adjusting the value with the variable resistor 41, the frequency deviation on the + side (+Δf
) can be adjusted accurately.

2b Data When Sl is rr L I+ At this time, the gate signal s5 is "H"', and the gate signal S
3 and 84 are L''. Therefore, the switch 56 is conductive,
The switches 52 and 54 are cut off and the low voltage V1 is output.

Therefore, by adjusting the value with the variable resistor 43, it is possible to accurately match the frequency deviation (-Δf) on one side, which is shifted by the same frequency Δf as described above.

If such voltage adjustment processing is performed, the modulation spectrum can be made symmetrical even if the characteristics of the VCO 18 are nonlinear.

By the ternary modulation signal S6 obtained in this way, V
When COl,8 is modulated, the output signal SO shown in FIG. 4G is obtained.
or can be obtained. Although the waveform of this output signal SO is slightly distorted at its rise and fall, the variable voltage V2
There are no biased changes in the upper and lower levels.

Further, even if the control voltage vs. frequency characteristic of the VCO 18 is nonlinear, a vertically symmetrical frequency shift can be obtained by adjusting the voltage level.

In other words, when a ternary modulation signal is used, even if the PLL modulator 10 has a low-frequency cutoff characteristic, the output signal So is not substantially affected by it, and the modulation has good adjustability against frequency deviation. Spectral characteristics can be obtained.

By the way, as the output voltage generating means 60, the variable resistor 4
If only 1 to 43 are connected in series, as shown in Figure 5, there is a possibility that the adjustment range of the variable resistor 41 will exceed the voltage V3 that outputs the frequency (f + △f) that indicates a frequency deviation on the + side. There is.

In such a case, output voltage generating means 60 as shown in FIG. 6 may be used.

The figure shows two variable resistors 62, 63 and two fixed resistors 61, 64 connected in series, and one variable resistor 67 and two fixed resistors 66, 68 connected in series. are connected in parallel, the variable resistor 62 outputs a higher voltage V3, and the variable resistor 63 outputs a lower voltage V1. Then, a medium voltage from the variable resistor 67
2 can be output.

With this configuration, as shown in FIG. 5, the adjustment ranges of the respective output voltages V1 to V3 can be overlapped, so that the parallel shift of the characteristics depending on the temperature of the VCO 8 or
It is possible to sufficiently respond to changes in inclination.

[Effects of the Invention] As described above, according to the present invention, a binary signal can be converted into a ternary signal, and when this is used as a pulsed modulation signal of a VCO, the PLL type modulator can cut off the low frequency range. Even if the low-frequency cut-off characteristic is present, the output signal will not be substantially affected, and waveform distortion due to the low-frequency cutoff characteristic can be eliminated.

Even if the control voltage vs. frequency characteristic of the VCO is nonlinear, the modulation frequency and frequency shift can be adjusted accurately and independently, so symmetry of the modulation spectrum can be obtained.

Therefore, the present invention is extremely suitable for application to mobile radio equipment using the above-mentioned PLL type modulator.

[Brief explanation of drawings]

FIG. 1 is a system diagram of a PLL type modulator to which this invention is applied,
Fig. 2 is a connection diagram showing an example of the level conversion circuit according to the present invention, Figs. 3 to 5 are diagrams for explaining its operation, Fig. 6 is a connection diagram of the output voltage generating means, and Fig. 7 is a connection diagram of the conventional example. Genealogical diagram, No. 8
1.0 to 1.0 are explanatory diagrams of the operation. 10 ・ 18 ・ 30 ・ 34 ・ 40 ・ 48゜52゜58 ・ 60 ・ 70 ・ 80 ... PLL type modulator ... VCO ... Modulation signal forming circuit ... Enable signal generation circuit ... Level conversion circuit・・AND circuit 54.56 ・・・Switch・・・Buffer (filter) ・・Output voltage generation means・・Switching means・・Gate signal formation means ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・

Claims (1)

[Claims] (1) A data signal that repeats at binary levels of logic "1" and "0" and an enable signal that maintains a constant level for the period during which this data signal is obtained are converted to a three-level data signal. In the level conversion circuit, output voltage generating means generates output voltages in three stages of high level, middle level, and low level, switching means sequentially selects any one of these three stages of output voltages, gate signal forming means for forming a gate signal for the switching means, the medium voltage is selected as the output voltage when the data signal is not input, and the high voltage is selected as the output voltage when the data signal is logic "1". and the gate signal forming means is logically configured to convert the data signal into a ternary level data signal by selecting the low voltage as the output voltage when the logic is "0", and A level conversion circuit characterized in that each of the output voltages can be finely adjusted.