JPH0447760U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the memory control circuit of the present invention, and FIG. 2 is a time chart showing an example of signal states mainly in the DMA controller. 1... Central processing unit, 2... DMA controller, 3... Real memory, 4... Expansion memory, 11...
... Latch circuit, 12 ... Read control section, 13 ... Write control section, 20 ... Switch control circuit.

Claims (1)

[Claims for Utility Model Registration] 1. Expansion memory for storing at least one of the program and data in a memory control circuit when a general-purpose central processing unit saves the program and data outside the real memory for program execution. and a DMA controller that directly controls data transfer between the real memory and the expanded memory.
A switching control circuit that switches and sets the read signal and write signal output by the DMA controller to either the real memory side or the extended memory in accordance with the operation timing of the central processing unit and the DMA controller, and from the real memory to the extended memory. , and a transfer direction control latch circuit that specifies a timing operation according to a preset program that specifies the data transfer direction from the extended memory to the real memory. 2. The switching control circuit according to claim 1 includes two NOT circuits that input read signals and write signals from the DMA controller, and two control signals for reading and writing from a transfer direction control latch circuit. and two control inverting circuits, each of the read signal and write signal outputted through the inverting circuit, and the reading and writing of the control signal, and the respective outputs as the read signal and the write signal. two real memory NAND circuits that output to the real memory as
2, which inputs each of the read signal and write signal outputted through the above-mentioned inverting circuit, and each of the reading and writing signals of the control inverting circuit, and outputs the respective outputs as a read signal and a write signal to the extended memory. 2. The memory control circuit according to claim 1, having a logic circuit configuration including two expansion memory NAND circuits.