JPS6020099U - P-ROM writer - Google Patents
P-ROM writerInfo
- Publication number
- JPS6020099U JPS6020099U JP10971183U JP10971183U JPS6020099U JP S6020099 U JPS6020099 U JP S6020099U JP 10971183 U JP10971183 U JP 10971183U JP 10971183 U JP10971183 U JP 10971183U JP S6020099 U JPS6020099 U JP S6020099U
- Authority
- JP
- Japan
- Prior art keywords
- rom
- data
- circuit
- roms
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例のブロック図である。
図において、１・・・・・・ＣＰＵ・バス制御部、２・
・・・・・システムメモリ、３・・・・・・シリアル回
線インターフェース、４・・・・・・キーボード及びデ
ィスプレイ制御部、５・・・・・・バッファメモリ、６
・・・・・・書込み・読出し制御回路、７・・・・・・
アドレスデータ用ｐｔｏ、ｉｉ・・・・・・入出力デー
タ用ＰＩＯ１１２・・・・・・比較照合回路、１３・・
・・・・ｐ−ＲＯＭ実装用ソゲット、２１・・・・・・
書込パルス用電圧制御回路、４１・・・・・・キーボー
ド、４２・・・・・・デイスブｌ／イ、６１・・・・・
・ｐ−ＲＯＭ選拓スイッチ、である。FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1... CPU/bus control unit, 2...
...System memory, 3 ... Serial line interface, 4 ... Keyboard and display control section, 5 ... Buffer memory, 6
...Write/read control circuit, 7...
PTO for address data, ii... PIO112 for input/output data... Comparison verification circuit, 13...
...Soget for p-ROM mounting, 21...
Write pulse voltage control circuit, 41... Keyboard, 42... Disable L/I, 61...
- It is a p-ROM selection switch.
Claims (1)
Ｍという）を実装するソケットとこれらｐ−ＲＯＭへデ
ータを入出力する入出力回路と各Ｐ−ＲＯＭへの入出力
データを比較する比較照合回路とを各Ｐ−ＲＯＭ単位に
備え、前記各Ｐ−ＲＯＭへの異ったデータを記憶するバ
ッファメモリと、前記各ｐ−Ｒ，ＯＭへのアドレスデー
タを生成するアドレス回路と、前記各ｐ−ＲＯＭへのデ
ータ書込みおよびデータ読出しを制御する制御回路と、
これら各回路を制御して前記各ｐ−ＲＯＭに割当てられ
たアドレスに従って各ｐ−ＲＯＭにそれぞれ所定データ
を同時に書込ませるプロセッサ回路とを備えることを特
徴とするｐ−ＲＯＭ書込器。Multiple programmable read-only memories (p-RO)
Each P-ROM is equipped with a socket for mounting the P-ROM, an input/output circuit for inputting/outputting data to and from these P-ROMs, and a comparison/verification circuit for comparing input/output data to each P-ROM. - A buffer memory that stores different data in the ROM, an address circuit that generates address data for each of the p-Rs and OMs, and a control circuit that controls data writing and data reading to each of the p-ROMs. and,
A p-ROM writer comprising: a processor circuit that controls each of these circuits to write predetermined data into each p-ROM at the same time according to the address assigned to each of the p-ROMs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10971183U JPS6020099U (en) | 1983-07-15 | 1983-07-15 | P-ROM writer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10971183U JPS6020099U (en) | 1983-07-15 | 1983-07-15 | P-ROM writer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020099U true JPS6020099U (en) | 1985-02-12 |
Family
ID=30255457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10971183U Pending JPS6020099U (en) | 1983-07-15 | 1983-07-15 | P-ROM writer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020099U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62229216A (en) * | 1986-02-12 | 1987-10-08 | アイメトリックス ― システムズ アクチエンゲゼルシャフト | Temple for spectacles |
-
1983
- 1983-07-15 JP JP10971183U patent/JPS6020099U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62229216A (en) * | 1986-02-12 | 1987-10-08 | アイメトリックス ― システムズ アクチエンゲゼルシャフト | Temple for spectacles |
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