JPH0447786B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic signal measuring device, and more particularly, to a logic signal measuring device for displaying at least one logic signal as a waveform on a display device such as a CRT (cathode ray tube) in response to a predetermined combination of a plurality of digital trigger signals. related to a device for

Prior Art Logic signals are commonly measured using logic analyzers. A logic analyzer has a plurality of comparators that compare an input logic (digital) signal to a controllable threshold at predetermined time intervals (sampling clock periods). The digital output from the comparator is stored in storage means such as RAM (Random Access Memory) and displayed on display means such as CRT.

However, with logic analyzers, the input digital signal and sampling clock pulses are not synchronized, making it extremely difficult and sometimes impossible to display waveform details and glitches such as spikes and linking. It was hot. This traditional problem is solved by using a wideband oscilloscope. However, when using a regular oscilloscope, it is necessary to trigger the time domain circuit or sweep generator with a complex combination of multiple digital input trigger signals in order to obtain a stable display of logic signals and efficient signal analysis. Therefore, the above-mentioned conventional problems are not solved.

OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a logic signal measuring device that has the features of both an oscilloscope and a logic analyzer.

Another object of the present invention is to provide a logical signal measuring device capable of operating a time-base circuit using various logical combinations of a plurality of trigger signals.

Yet another object of the present invention is to provide a logic signal measuring device having trigger signal indicating means for indicating a selected combination of trigger signals.

Still another object of the present invention is to provide a logic signal measuring device having an indicating means for indicating a selected logic combination in a plurality of colors depending on the selection of related circuits or control circuits.

Summary of the Invention A digital signal measuring device according to the present invention includes one or more vertical analog channels corresponding to the circuit of a conventional oscilloscope, and a logical trigger that triggers the time axis by a logical combination selected from a plurality of input trigger signals. and a control circuit. Upon occurrence of a selected trigger pattern or series of digital trigger signals, the time base circuit operates to display the input digital signal applied to the input of the vertical channel. Furthermore, the digital signal measuring device according to the present invention has an instruction means for indicating the selected trigger signal. This indicating means has a plurality of indicating elements (each including a plurality of LEDs (light emitting diodes), etc.) arranged in a matrix, and each indicating element emits a different color (for example, red and green).

DESCRIPTION OF THE EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a simple block diagram for explaining a logic signal measuring device according to an embodiment of the present invention. In FIG. 1, the digital input signal under test is applied to input terminal 10 either directly through a coaxial cable (not shown) or through a passive voltage probe 38.
It is added to a,...,10n. Input terminal 10a,
..., 10n is applied to the vertical deflection plate of the CRT 20 via the vertical axis circuit. The vertical axis circuit consists of an input circuit 12 (circuits 12a, . . . , 12n, each having a step attenuator and a buffer amplifier, and a probe 10).
a,...,10n), vertical axis amplifier 1
4, a channel switch circuit (or multiplexer) 16, a vertical axis output amplifier 18, and the like. On the other hand, the time axis circuit includes a trigger comparator 22,
It includes a threshold generator 24 (comprising a plurality of controllable threshold voltage generators 24a, . . . , 24n), a trigger control logic 26, a sweep generator 28, and a horizontal output amplifier 30. Passive voltage probe 38
has a plurality of voltage probes, each voltage probe having a probe tip 40, a series resistor 42, and a controllable offset voltage source 44. 1st
The logic signal measuring device shown in the figure further includes a DVM32
This DVM 32 has a multiplexer 34
a threshold voltage generator 24a, applied via a
..., 24n and the controllable offset voltage of a passive voltage probe 38 applied via input terminal 36.

Next, the operation of the circuit shown in FIG. 1 will be explained. The digital input signals applied to the input terminals 10a, . . . , 10n are attenuated to a predetermined value according to the input level by the step attenuators of the input circuits 12a, . The vertical axis amplifier 14 amplifies the input signal from the corresponding input circuit to a predetermined value. Although not shown in Figure 1, the display surface (screen) of the CRT20
In order to control the vertical position of the waveform displayed on the screen, it is desirable to control the DC level of the input signal by a DC level (or vertical position) control circuit. The output signals from the vertical amplifiers 14a, . . . , 14n are selectively applied to the vertical output amplifier 18 by a channel switch circuit 16 controlled by a switch control signal. That is, the channel switch circuit 16 is controlled by a switch control signal and selectively outputs one or more of the input signals in a time-division manner. The push-pull output from the vertical axis output amplifier 18 is applied to the deflection plate of the CRT 20 to control the vertical deflection of the electron beam according to the input signal.

A trigger comparator 22 having a plurality of comparators 22a, . . . , 22n converts the outputs of the input circuits 12a, .
..., 24n, and when the signals from the input circuits 12a,..., 12n exceed the respective thresholds in the positive and negative directions, positive and negative pulse edges are generated, respectively. . The bistable output from trigger comparator 22 is applied to trigger logic control circuit 26, which includes various logic gates. Trigger logic control circuit 26 outputs a trigger signal when the digital input signal matches a predetermined logic pattern or digital word. Details of the trigger logic control circuit 26 will be described later. Trigger pulses from trigger logic control circuit 26 are applied to a sweep generator 28, which is conventional in the art. The sweep generator 28 outputs a gradient wave signal, which is amplified to a predetermined value in the horizontal axis output amplifier 30, converted into a push-pull signal, and applied to the horizontal deflection plate of the CRT 20. CRT
The 20 electron beams are horizontally deflected at a predetermined repetition rate in response to a gradient signal.

In addition, one or more external trigger signals can be input to input terminal 2.
7 to the trigger logic control circuit 26 and to the channel switch circuit 16 to control the sweep generator 28. At the same time, it is also possible to display the applied external trigger signal on the CRT 20. Furthermore, it is also possible to add a portion of the output signal of the trigger logic control circuit 26 to the vertical axis circuit and display on the CRT 20 only the trigger pulse or the trigger pulse and the input signal simultaneously.

Next, the input impedance of the input circuits 12a, . . . , 12n viewed from the input terminals 10a, . Input terminals 10a,...,
Passive voltage probe 38 connected to 10n has series connected resistors 42a, . . . , 42n and variable offset voltage sources 44a, . Series resistor 42 and the input resistances described above constitute a voltage divider or attenuator as viewed from the signal source connected to probe tips 40a, . . . , 40n. If the resistance value of the series resistor 42 is selected to be 450Ω, the input resistance value of the probe tip 40 increases to 500Ω, which reduces the load on the signal source and also reduces the load on the input terminal 10.
The amplitude of the signal applied to a,...,10n is set to 1/10 of the actual value. Offset voltage source 44a,
By changing the voltage values and polarities of ..., 44n, high-speed logic signals such as ECL can be detected with high fidelity. In one specific example, the variable range of the offset voltage source 44 was appropriately from -5 to +5V.

The DVM 32 includes a threshold voltage generator 24a,
..., 24n is used to digitally measure the threshold value V _T applied. These thresholds can be measured continuously using multiplexer 34. For example, when using a 10:1 passive voltage probe 38, the measured voltage is automatically multiplied by 10 to V _T using a suitable known sensor, and the measurement result at each threshold voltage is calculated. is stored in the storage means.
Additionally, DVM 32 has input terminals 36 that connect to probe tips 40a, . . . , 40n to compensate for offset voltages at passive voltage probes 38. That is, the output voltage of the input circuits 12a, . (i.e. (Vin-Vo)A). When measuring the threshold voltage in consideration of offset voltage compensation, the probe tip 40a is
It connects to input terminal 36 of DVM 32 and measures an offset voltage V ₀ that is added to the voltage that is compared with the voltage from threshold generator 24a. Therefore,
These threshold voltage V _T and offset voltage Vo allow the DVM 32 to indicate the accurate threshold voltage at the probe tip 40. The above procedure is shown in the flowchart of FIG. That is, in Fig. 2, first the threshold voltage V _T is measured, then the offset voltage Vo is measured, and finally (V _T +Vo)
is calculated and the threshold voltage (V _T +Vo)) at the probe chip 40 is displayed.

3A and 3B illustrate a preferred embodiment of the trigger logic control circuit 26 shown in FIG. 1. In FIG. 3A, the n-channel logic input signal CH1,
..., CHn are applied to n input terminals of an OR gate 54 and an AND gate 56 through polarity selection means including an inverter 50 and a selection switch 52, respectively. The outputs of OR gate 54 and AND gate 56 are output from output terminals 58a and 58, respectively.
It is taken out from b. If it is necessary to add a "don't care" function that disables the logic circuit described above, select switches 52a,...,52n
Add two terminals to each of the OR gates 54
and “low” and “high” for AND gate 56, respectively.
It is sufficient to apply a logic signal of the level.

The logic circuit shown in FIG. 3A has an input logic signal
When the word pattern consisting of CH1, ..., CHn matches the specific word pattern preset by the selection switches 52a, ..., 52n,
Outputs trigger pulse. For example, assuming that the number of channels is 4, there are combinations of AND triggers such as CH1, CH2, CH3, CH4, CH1, CH2, CH3, 4, etc., and OR trigger outputs, such as CH1+CH2+CH3+CH4, 1+CH2+CH3+CH4, etc. Furthermore, there are combinations such as CH1・CH2+CH3・CH4, 1・CH2+3・CH4, etc. as triggers for combinations of AND and OR. Note that "." indicates a logical product operation, and "+" indicates a logical sum operation. Signal CH1,
CH2, CH3, and CH4 are logic signals directly input to the OR gate 54 and the AND gate 56, and signals 1, 2, 3, and 4 are inverted by the inverter 50 and then input to the OR gate 54 and the AND gate 56. This is a logic signal to be input. For example, AND trigger CH1, CH2, CH3, CH4
Now, when all four logic input signals become high level (in the case of positive logic), a trigger pulse is output from the output terminal 58b. In other AND triggers, such as 1, CH2, CH3, and CH4, when the input signals of all channels other than channel 1 become high level, a trigger pulse is output from the output terminal 58b. Similarly, OR trigger CH1+CH2+
For CH3+CH4, when the input signal of any of the four channels becomes high level, a trigger pulse is output from the output terminal 58a.

Additionally, a combination trigger pulse, e.g.
In the case of CH2+CH3/CH4, a pair of AND gates 60, 62 and an OR gate 64 may be used, as shown in FIG. 3B. In the case of a combination trigger pulse as well, a trigger pulse is output from the output terminal 66 when a predetermined logic pattern is input. Note that the polarity selection circuit shown in FIG. 3A is replaced by the polarity selection circuit shown in FIG.
It may also be provided in the logic circuit shown in the figure.

By the way, the logic function can be controlled by one control means and one control means.
If the selection is made using a separate microprocessor (or similar circuit), there is a problem in that the selected logic function cannot be displayed unless a means for storing the selected logic function is provided. This problem is 4A
This problem is solved by using the indicating means according to the invention as shown in FIGS. and 4B.

As shown in FIGS. 4A and 4B, the indicating device according to the present invention includes a plurality of indicating elements L1a, L1
b, L1c,..., L1n, and L2a, L2b,
L2c, . . . , L2n are arranged in a matrix. Each indicator element includes two LEDs (light emitting diodes) 72, 7, as shown in FIG. 4A.
4 (each emits different colors, e.g. red and green)
is stored in a translucent container 70. The upper part (in the drawing) of the container 70 (that is, the part disposed on the operator's side) preferably has a rough surface so as to diffuse light and provide a uniform light emitting surface. The plurality of indicating elements L1a to L1n and L2a to L2n are
They are arranged in a matrix on the front panel of the logic signal measuring device as described above, and constitute an indicating means. The number of pointing elements in each column of the matrix is equal to the number of vertical input channels (eg, 4).

The trigger logic setting procedure is as follows.

(1) First, using a common control switch (not shown), set the selection switch 52a to either "high level" (H), "low level" (L), or "don't care" (X). to activate channel 1 (CH1). When the selection switch 52a is set to (H) or (L), a current flows from a control circuit (not shown) to the LED 72 or 74 of the indicating element L1a depending on the setting state, and the LED 72 or 74 emits light. Furthermore, when the selection switch 52a is set to (X), the indicating element L1a
No current is supplied to (ie, none of the LEDs emit light).

(2) Next, set the selection switch 52b to (H), (L) or (X)
Set it to one of the following to activate channel 2 (CH2).

(3) Repeat the above procedure up to channel n and cause the LED of the first example of the indicating device to emit light according to the set AND trigger logic mode.

In this way, for example, for certain trigger logic modes CH1, CH2,..., CHn, the indicating elements L1a, L1b,..., L1n are set to R, R,..., respectively.
R (R indicates red light emission), while another trigger logic mode CH1, CH2..., CHn is set to G, R,
..., R (G indicates green light emission). In this manner, the selected trigger logic mode can be easily indicated or displayed.

In logical signal analysis, for example (CH1, CH2,
It is often necessary to trigger the time axis by taking the OR of two logical operation results, such as CH3・CH4)+(1・2・CH3・CH4). Such a combination trigger logic mode can be obtained using the trigger logic circuit described with reference to FIG. ..., displayed on L1n, and the second
The trigger logic mode of is displayed on the second row of indicating elements L2a, L2b, . . . , L2n of the indicating device. still,
In the above example, the indicator elements other than indicator elements L2a and L2b are caused to emit red light.

Effects of the Invention The logical signal measuring device according to the present invention provides at least one signal for one logical combination of a plurality of trigger signals.
1 input signal can be displayed as a waveform. The use of a multi-color indicating device allows the selected trigger logic mode to be displayed in a very small space, helping to reduce device size and prevent measurement errors. Additionally, the selected complex trigger logic mode can be determined at a glance. Furthermore, since a multiplexer and a digital voltmeter are provided, each threshold value can be measured. Further, even if a passive voltage probe having an offset voltage source is used, it is possible to easily determine the actual threshold value of the probe chip in consideration of this offset voltage.

Modifications and Modifications of the Invention Although preferred embodiments of the present invention have been described above, the embodiments described above do not limit the gist of the present invention, and those skilled in the art will be able to make various modifications and changes based on the embodiments described above. can be done.

The LEDs serving as indicating elements may be arranged in two rows in the horizontal direction. Furthermore, the display of the indicating element need not be limited to two colors, and furthermore, different light emitting colors may be used for each indicating element. The trigger pulse is generated in response to a selected logic state, but may be designed to trigger on a particular edge (positive or negative edge) of a given input signal (pulse). In such an end trigger mode, the indicating element is designed to flash when triggered, and the flash allows easy confirmation of the triggering point.

[Brief explanation of the drawing]

1 is a simplified block diagram illustrating one embodiment of a logic signal measuring device according to the present invention; FIG. 2 is a flow diagram illustrating the steps for generating a compensated threshold;
Figures 3A and 3B show one of the trigger logic control circuits.
FIGS. 4A and 4B are block diagrams showing an embodiment of the present invention, and are diagrams showing trigger signal indicating means that can be applied to a logic signal measuring device according to the present invention. 12: input circuit, 20: cathode ray tube, 26: trigger logic control circuit, 32: digital voltmeter (DVM), 34: multiplexer, 70: indicating means, L1a to L1n, L2a to L2n: indicating element.

Claims (1)

[Claims] 1. A plurality of trigger comparators compare a plurality of input signals with threshold values to generate a plurality of digital input trigger signals, and a trigger control logic circuit compares the plurality of digital input trigger signals to a predetermined value. A multiplexer for selecting one of the threshold values for the plurality of comparators in a logic signal measuring device that detects when a logical combination state of and a digital voltmeter for measuring the threshold voltage selected by the multiplexer, and a plurality of indicating elements each representing a selection state corresponding to each digital input trigger signal of the above logical combination in a different color is arranged in a matrix of a plurality of rows and a plurality of columns. the number of indicating elements along one of the rows and columns of the matrix is equal to the number of digital input trigger signals, and the indicating elements along one of the rows and columns indicate the selected state of the logical combination. an instruction means is provided to set the selection states of the logical combinations as many times as there are rows and columns of the matrix, and when the plurality of digital input trigger signals match any one of the selection states of the logical combinations; A logical signal measuring device characterized in that the logical signal measuring device displays a waveform of at least one of the above-mentioned input signals in response to the above.