JPH0447811A - Pulse summing-up counter circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a pulse total counter circuit that obtains a total value of the number of pulses of a plurality of synchronized pulse signals input in parallel, the number of pulses included in many pulse trains can be calculated using a small-scale circuit. In a pulse aggregation counter circuit that obtains an aggregate value of the number of pulses of multiple synchronized pulse signals that are input in parallel, the pulses included in the pulse signal are counted over time for each unit period of the pulse signal. a pulse adjustment unit that converts into discrete pulses on the axis to obtain a single pulse train;
A counter that counts the number of pulses in a single pulse train.

[Industrial Application Field] The present invention relates to a pulse total counter circuit that obtains a total value of the number of pulses of a plurality of synchronized pulse signals input in parallel.

[Conventional technology]

In systems that multiplex and transmit multiple channels, the quality of the transmission path (
pit error rate) is measured. In such a device for measuring transmission quality, a total value of a plurality of error bits obtained for each channel is obtained in synchronization with a predetermined clock signal using a pulse total counter circuit.

FIG. 6 is a diagram showing the configuration of a conventional pulse total counter circuit.

In the figure, a plurality (=n) of pulse trains given in synchronization with a predetermined clock signal are processed by a counter 61 . ~61. is given, and the number of pulses included in each pulse train is determined individually. counter 61+
, 61g is the count value output from full adder 62.
The counter 61 . ~61
The count values output from 7 are a combination of two full adders 62□ to 62. , is added by . Further, the outputs of these full adders are sent to the full adders 62 . . . , which are connected in multiple stages by combining two full adders until a single sum is obtained. %-1+1~62. ．． are added sequentially by
A total value of the number of pulses included in all pulse trains is calculated.

[Problems to be Solved by the Invention] By the way, such a conventional pulse total counter circuit requires a number of counters and full adders corresponding to the number of input pulse trains, and if the required number of counts is large, The bit length of each full adder becomes a large value. Therefore, when the number of input pulse trains and the number of counts are large, the circuit size is also large.

An object of the present invention is to provide a pulse total counter circuit that can obtain a total value of the number of pulses included in many pulse trains using a small-scale circuit.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, a pulse total counter circuit obtains a total value of the number of pulses of a plurality of synchronized pulse signals input in parallel.

The pulse adjustment unit 11 converts pulses included in a plurality of pulse signals into discrete pulses on the time axis for each unit period of the pulse signal, thereby obtaining a single pulse train.

Counter 13 counts the number of pulses in a single pulse train.

[For production]

In the present invention, the pulse adjustment section 11 converts pulses included in a plurality of synchronized pulse signals inputted in parallel into discrete pulses on the time axis for each unit period of the pulse signal, and converts the pulses included in a plurality of synchronized pulse signals input in parallel into discrete pulses on the time axis. obtain.

The counter 13 counts the number of pulses in the single pulse train obtained.

The pulse adjustment unit 11 requires a small scale circuit for each unit pulse signal light to obtain a single pulse train, and when the number of input pulse signals is large, it is expanded by adding a similar circuit. It can be configured by Further, the number of counters 15 may be one regardless of the number of input pulse trains.

Therefore, it is possible to realize a pulse tally counter that can input a large number of pulse signals using a small-scale circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In the figure, the pulses included in pulse train A are generated by a monostable multivibrator (hereinafter referred to as "monomulti") 2.
1. , and MonoMulti 211! via orgate 2
2 to the first input. The pulses included in the pulse train B are applied to the second input of the OR gate 22 via the monomulti 21□1 and the monomulti 21°. The pulses included in the pulse train C are applied to the third input of the OR gate 22 via the monomulti 21,1 and the monomulti 21st. The output of the OR gate 22 is the output of the counter 2
Connected to 3. The counter 23 has pulse trains A, B, and C.
Outputs the total number of pulses included in .

FIG. 3 is an operation timing chart of this embodiment.

The operation of this embodiment will be described below with reference to FIGS. 2 and 3.

Each pulse included in the pulse train A and BSC is inputted in synchronization with a predetermined timing (Fig. 3).

Each pulse included in the pulse train A is a monomulti 21 I
A predetermined delay time τ1. is given (Figure 3 ■
), the pulse width τ, by the monomulti 214.

is converted into a pulse of Each pulse included in the pulse train B is given a predetermined delay time τ21 by the monomulti 21t.
is given (Fig. 3), and is converted into a pulse with a pulse width τ by the monomulti 21o.

Each pulse included in the pulse train C is a monomulti 213,
The predetermined delay times τ and l are given by (Fig. 3 ■)
, Monomulti 213! It is converted into a pulse with a pulse width τ, I□. In this way, monomulti 21++, 2
1tr, delay time τ11 given by 2131,
τold and τold are as follows, where T is the maximum period of the input pulse, τ1l=T/7, τ□=3T/7, τ31=5T
/7 is set to the value given by the formula. Further, the pulse widths τ4, τ0, τ of the pulses output from the monomulti 21°, 21□2.21xx are all set to T/7.

Therefore, the pulses included in each period of each pulse train are:
This is converted into discrete pulses separated by 2T/7 on the time axis and obtained as the output of the OR gate 22. counter 23
counts the pulses thus obtained, and obtains the total number of pulses of the pulse trains ASB and C.

Note that this embodiment is also applicable to cases where the number of input pulse trains is other than "3".

That is, in order to apply this embodiment when the number of pulse trains is n, the monomulti 211I corresponding to each pulse train must be
21□ and 21□ to 2In□ are provided, the number of input terminals of the OR gate 22 is set to n, and the number of bits of the counter 23 is set to a predetermined value. Also, mono multi 218. The delay time τ11~τ□ given by ~21□ is set to a value expressed by the general formula r+u=(2k l)T/(1+2n), and the monomulti 21. T~21fi!
The time constants of are all set equally to T/(1+2n). Note that k indicates any of the values ("1" to "n") corresponding to the reference numbers of the monomultis 21□ to 2111I.

In this way, according to this embodiment, the total number of pulses included in a plurality of pulse trains input synchronously can be calculated using a simple circuit. Furthermore, in this embodiment, even when the number of pulse trains or the maximum total value is large, the full adder required in the conventional configuration is not required, and the number of required counters is a single number regardless of the number of pulse trains. It is. That is, for example, if the number of pulse trains is r 10
0J, the conventional configuration required 100 counters and 99 full adders, but this embodiment requires a single counter, a single OR gate, and 100 full adders.
Since the pulse adjustment circuit is composed of three pulse adjustment circuits, the circuit scale can be reduced to about 1/2 J compared to the conventional configuration, even if it is assumed that the circuit scale of each of these parts is the same.

FIG. 4 is a diagram showing another embodiment of the present invention.

In the figure, pulse train A is connected to the first input terminal of OR gate 41 and AND gate 42 . is given to one input of Pulse train B is applied to the second input terminal of OR gate 41 and one input of AND gate 42□. The pulse train C is applied to the third input terminal of the OR gate 41 and one input of the AND gate 42°. or gate 4
1 output is mono multi 43. is input. The inverted output direction of the monomulti 43 is connected to the input of the mono multi 43□ via a delay buffer 441. mono multi 43
The inverted output direction of □ is via the delay buffer 44 and the mono multi-channel 43. connected to the input of Monomulti 43. The non-inverted output Q of AND gate 42. is connected to the other input of The non-inverting output Q of the monomulti 43□ is connected to the other input of the AND gate 42□. Monomulti 43.
The non-inverted output Q of AND gate 42. is connected to the other input of anime) 42. ．． The respective outputs of 42g and 423 are connected to the input of the counter 23 via the OR gate 22.

FIG. 5 is an operation timing chart of this embodiment.

The operation of this embodiment will be described below with reference to FIGS. 4 and 5.

Each pulse included in the Hough L/S sequences A, B, and C is input synchronously (Fig. 5 (■)). The OR gate 41 triggers the monomulti 43 □ in response to a pulse included in any one of the pulse trains ASBSC (Fig. 5 ■), and its inverted output direction becomes low level. Mono multi 43□ is mono multi 4
3. When the inverted output direction of the delay buffer 44. Furthermore, when the inverted output direction of the mono multi 43□ returns from a low level to a high level (■ in Fig. 5), the mono multi 43° is triggered via the delay buffer 4 (■ in Fig. 5).
4. (Fig. 5, ■).

By the way, in this embodiment, if the maximum period of the input pulse is T, then the monomulti 43. ~43° time constant τ,
~τ3 are all set to less than 774, and the delay buffer 44. ．． The delay times D+ and Dz of 44g are both T/
(4$2), so monomulti 43. ~4
3. Each of the non-inverted outputs Q becomes high level at different timings within a half cycle (=T/2).

Therefore, when the duty ratio of each pulse included in the pulse train A and ESC is 50%, the AND gates 421 to 42. The pulses are converted into discrete pulses on the time axis (Fig. 5, ■ to ■), which are further synthesized by the blue gate 22 and converted into a single bit string. counter 2
3 counts the pulses of the single bit string obtained;
A total value of the number of pulses included in pulse trains A, B, and C is obtained.

Note that in this embodiment, the number of input pulse trains is
It is also applicable to cases other than 3. That is, in order to apply this embodiment when the number of pulse trains is n, the number of input terminals of the OR gates 41.22 is set to n, and the number of AND gates 42+ to 427 and mono-multiple 43. ~43fi and delay buffer 44. ~44
．． ．． is provided, and the number of bits of the counter 23 is set to a predetermined value. Furthermore, monomulti 43. The time constant τ of ~43 is
τ=T/(1+n) The delay buffer 44, ~
441. -+ delay time, "'D11-." is DI
=Dt ・ =D, -+ =T/(4 times (1+n
)) to the value shown by the formula.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of pulse trains input synchronously and in parallel can be processed using a circuit that is simpler than the conventional configuration and can be easily applied even when the number of pulse trains and the maximum total value are large. The total number of pulses can be obtained.

Therefore, a pulse tally counter circuit with a large number of input pulse trains and a large maximum tally value can be realized using a small-scale circuit.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is an operation timing chart of this embodiment, and Fig. 4 is a diagram showing another embodiment of the present invention. 5 is an operation timing chart of this embodiment, and FIG. 6 is a diagram showing the configuration of a conventional pulse total counter circuit. In the figure, 11 is a pulse adjustment unit, 13.23.61I to 61n are counters, 21z, 21
□, 21□, 21□2.2110.21, 2.43t
, 43g, 43s are monostable multivibrators, 22.41 is OR gate, 42, . 42□, 423 are AND gates, 62, ~62
．． ．． is a full adder. Figure 3: Principle block diagram of the present invention. Figure 3: A diagram showing one embodiment of the present invention. Operation timing chart of this embodiment. Figure 3: Diagram showing another embodiment of the present invention.

Claims (1)

[Claims] (1) In a pulse aggregation counter circuit that obtains a total value of the number of pulses of a plurality of synchronized pulse signals input in parallel, the pulses included in the plurality of pulse signals are calculated on the time axis for each unit period of the pulse signal. Convert to discrete pulses,
A pulse totaling counter circuit comprising: a pulse adjustment section (11) that obtains a single pulse train; and a counter (13) that counts the number of pulses in the single pulse train.